Memory innovations can come from
adding exotic materials to otherwise-conventional cell
structures and CMOS processes or by coming up with new cell
structures. 
Whereas our near-term predictions are usually overenthusiastic, our far-term forecasts are often correspondingly too pessimistic. Plenty of examples of this phenomenon exist in high technology. Look, for example, at the delayed rollout of advanced digital-cellular-phone standards, much slower than most pundits predicted a few years back. In contrast, though, note how few cellular phones those same pundits, a few decades back, were saying we'd all be using at the turn of the century. 
Contact Technical Editor Brian Dipert at 1-916-454-5242, fax 1-530-937-8147, e-mail 
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Exotic memories, diverse approaches
Newfangled memory technologies come and go, but every once in a while, one makes it out of the laboratory and into your next design. All of these candidates aspires to be the next semiconductor success story. Which ones dreams will come true?
By Brian Dipert, Technical Editor -- EDN, 4/26/2001
Intel and its partners and competitors have arguably overestimated how quickly the PC-software vendors would develop applications that demand gigahertz-speed CPUs and how successfully those vendors would convince us to run those applications. But most of us have also by now heard the 1943 quotation from IBM Chairman Thomas Watson: 'There is a world market for maybe five computers.' Similar near-term overoptimism and long-term overpessimism plague the television industry. How few of you tune into digital TV signals today, but how few of your great grandparents envisioned a television or several in nearly every home at the new millennium? It's no surprise, then, that similar poor forecasting plagues the memory industry. DRAM manufacturers and memory-standards bodies have been talking about DDR (double-data-rate) SDRAM since the mid-1990s, but manufacturers have only recently begun to ship chips in any semblance of volume and then only on graphics cards, not as PC main memory ( Reference 1 ). Similarly, most followers of the high-tech industry are familiar with Direct RDRAM's (Rambus-dynamic-random-access-memory) setbacks. Meanwhile, most DRAM sold today is single-data-rate SDRAM that manufacturers defined more than a decade ago, and plenty of even older asynchronous DRAM still finds use in servers, workstations, and non-PC applications. Some initially hyped memory technologies never ended up amounting to much: Remember SLDRAM (SyncLink dynamic random-access memory), burst EDO (extended-data-out) DRAM, or bubble memory? Others end up coexisting, thriving in their respective application niches. The détente between DRAM and SRAM is a case in point ( Reference 2 ). But every decade or so, an upstart memory approach comes along that eventually displaces its predecessors. Look, for example, at what flash memory, which first emerged in the mid-1980s, has done to EPROM or what DRAM did to then-dominant core memory in the 1970s. Manufacturers of new memory technologies all hope to replicate these accomplishments. With your design decisions, you'll determine their ultimate success or failure. Nonvolatile newcomers DDR SDRAM and Direct RDRAM reflect, respectively, evolutionary and revolutionary approaches to improving memory bandwidth. Similarly, some new memory technologies stand on the shoulders of technologies which preceded them, whereas others take a clean-slate perspective on the challenge of creating the ideal approach. Toshiba's three-transistor NAND flash memory, due in mid-2002, is firmly in the evolutionary camp. Among NAND's strengths over the alternative NOR- and EEPROM-based flash-memory approaches has always been its comparatively small die for a given array density and manufacturing lithography ( Reference 3 and Reference 4 ). A multiple-bit transistor-chain structure, a multiplexed address bus, and few sense amplifiers and corresponding data I/O buffers are the key reasons for NAND's die-size and cost advantages, and NAND technology works well in many data- and file-storage applications. However, those same features make NAND unsuitable for fast-random-access and read-while-write applications, such as direct code execution. Toshiba supplies both NOR and NAND flash memory, and, in attempting to create an all-in-one device, the company Ironically, early NOR flash memory represented an evolutionary approach to the then-new flash-memory technology, which leveraged years of EPROM research and development, whereas NAND was a more revolutionary method of achieving low cost, nonvolatility, and in-system rewritability. Intel's StrataFlash memory, which currently stores 2 bits of data in each array transistor, is a further evolution beyond single-bit-per-cell NOR flash memory. (The company hopes to be at 4 bits per cell by the mid-decade.) Saifun Semiconductor, with partners Macronix, M-Systems, and Tower Semiconductor, is instead choosing to blaze a new path to 2 bits per cell with its NROM (nitride read-only memory). The NROM storage transistor is an otherwise-conventional n-channel MOSFET with an ONO (oxide-nitride-oxide)-trapping material instead of the normal gate dielectric ( Figure 1 ). Programming occurs with 9V applied to the shared word line; read operations apply 3V to the word line. The 4.5V on bit line 2 with bit line 1 grounded stores electrons in the nitride region corresponding to the first bit, and the 1.5V on bit line 1 with bit line 2 grounded enables read-back of bit 1's value. Swapping the bit-line-to-voltage correspondences enables the memory to program and read bit 2. The approximately 100Å-wide trapped-charge region means that the 2 bits don't affect each other; reading through one bit's trapped-charge region is possible. Silicon-dioxide layers that are 50Å thick or wider prevent oxide-damaging direct electron tunneling during bit writes, and only a few hundred electrons transfer during NROM programming, versus many thousands with floating-gate NOR flash memory. NROM erasing involves hole injection through the bottom oxide with holes generated by band-to-band tunneling. Adding NROM to a standard CMOS-logic process consists of applying the ONO layer after field isolation and before gate oxidation. A virtual-ground NROM array requires only two extra masking steps, plus two additional steps to create the high-voltage read and write transistors. Speaking of evolutionary nonvolatile, rewritable memories, what's going on with FRAM (ferroelectric random-access memory, Reference 6 )? In the roughly four years since FRAM replaces the DRAM capacitor's dielectric with a ferroelectric material, either a Perovskite crystal, such as PZT (lead-zirconate titanate), or a layered Perovskite, such as SBT (barium-strontium titanate). Ramtron favors PZT, which is to date the material in highest volume manufacturing. Ramtron's primary competitor, Symetrix, prefers SBT, whose advantages include a lack of highly mobile and semiconductor-processing-unfriendly lead ions. An externally applied electric field places the movable atom within the ferroelectric lattice in one of two positions ( Figure 2a ). The term 'ferroelectric' is a misnomer: FRAM neither contains iron material, nor relies on magnetic phenomena. FRAM, like ferro-magnetic memories, such as magnetic tape, hard drives, and MRAM (magnetoresistive RAM), simply exhibits a hysteresis effect ( Figure 2b ). FRAM reads, like DRAM reads, are destructive to the stored data. Therefore, FRAMs automatically rewrite cell contents after you read them, analogous to a DRAM's postread precharge delay. Unlike DRAM, though, FRAMs cannot perform unlimited write cycles. Instead, like EEPROM and flash memory, they exhibit 'fatigue' that extends the required write duration at high cycle counts and, ultimately, results in an inability to write or read valid data ( Reference 7 ). Whereas EEPROM and flash-memory cycle counts range into the millions of rewrites, FRAM specifications extend into the billions or trillions of cycles and possibly higher; it takes a long time to collect all that cycling data. However, keep in mind that because of the destructive-read phenomenon, FRAM-cycling specifications must comprehend To expand FRAM's operating margins at extended cycle counts and across wide temperature and voltage ranges, today's devices employ a redundant 2T2C cell. However, at February's ISSCC (International Solid-State Circuits Conference), Ramtron and Fujitsu announced that they'd developed a production-worthy, 1-Mbit FRAM, which, by using block-level redundancy, could employ 1T1C bit cells. Fujitsu's interest in FRAM is primarily for use as embedded memory arrays on ASICs; the company (along with Rohm) also serves as Ramtron's main discrete-chip foundry. Infineon (a Ramtron licensee) and Toshiba have also partnered on FRAM development, and Samsung, which also at this year's ISSCC presented a paper on a 0.6-micron-based, 4-Mbit chip, and others are also working on the technology. Aside from the lead-ion-mobility issue, other challenges of bringing an FRAM-enhanced CMOS process to high-volume status include ferroelectrics' sensitivity to common hydrogen and their intolerance of high wafer-processing temperatures. But, as DRAM manufacturers search for ways to continue to shrink their capacitor structures at 100-nm and smaller lithographies, ferroelectrics' high dielectric constants are becoming increasingly attractive. Dataquest estimated that by early 1999, the FRAM industry had spent less than $500 million on research and development, whereas the costs to develop a 1-Gbit DRAM might top $10 billion ( Reference 8 ). If FRAM could benefit from even a small portion of that DRAM research, its progress would greatly accelerate. Ironclad promises Ferroelectrics and other materials mimic the bipolar behavior of magnets (see sidebar 'Optical offshoots'). But why bother with a surrogate? Why not instead create storage structures based on magnetic materials? A small but growing number of companies have chosen this path, some employing the US government's DARPA financial assistance, because magnetic storage is Early MRAMs, like the core memories that preceded them, directly manipulated the storage elements with current-carrying wires ( Figure 3a ). The selected row and column lines each contained half the current necessary to flip a bit's magnetic polarity; together, they were sufficient to complete the task. Reading back stored data also employed inductive coupling. A current-created magnetic field interrogated the memory element, and the polarity of the induced voltages in a sensing circuit reflected whether a one or a zero was stored there. Think of this phenomenon as analogous to the stored data's giving greater or less resistance to the applied voltage and current. In applying single-cell results to multikilobit or multimegabit memory arrays manufactured in high volumes, MRAM vendors have had to surmount numerous obstacles. Magnetic resistance must not appreciably vary from one cell to another across the array. The resistance difference between parallel and antiparallel magnetic polarities must be significant to minimize sense delays and deliver fast read performance, and it must be stable across wide operating-temperature and voltage ranges. (Early approaches' difference between parallel and antiparallel magnetic polarities was less than 1%.) By moving from early anisotropic magnetic resistance to GMR (giant-magnetoresistive) techniques similar to those that today's hard drives employ, vendors such as Honeywell, IBM (the inventor of GMR), Micromem Technologies, Motorola, Nonvolatile Electronics, and Union Semiconductor have boosted the magnetic polarity-defined signal difference from roughly 0.5% to nearly 50%. The vendors have also moved to more elaborate cell structures as part of this improvement. The pseudo-spin valve contains two magnetic layers, one thinner, or 'softer,' than the other. To set the bit value, the chip applies sufficient current to the cell to, if necessary, flip the magnetic moment of the thicker, or 'harder,' layer. Reading a pseudo-spin-valve cell is a multipart process. First, the memory sets the thinner magnetic layer to one polarity state via a weaker current that doesn't disturb the thicker layer's state, and it senses the resistance of the cell. Then, it flips the magnetic moment of the thin layer and repeats the read. Comparing the two measured resistances indicates the thicker layer's polarity. In the spin-valve cell, one of the two layers is 'pinned,' or fixed, to a permanent, known polarity. This approach eliminates both interim writes and one of the two reads. For both spin-valve and pseudo-spin-valve cells, the interlayer between the two magnetic layers can be either a nonmagnetic, highly conductive material, such as copper, or a low-conductive dielectric that relies on magnetic tunneling to write the 'hard' layer. Resistance measurement can take place either through the GMR stack's height or along its width. At February's ISSCC, Motorola announced a functional 256-kbit MRAM with highly uniform resistance across the array, built on a 0.6-micron, five-layer-metal, dual-layer-polysilicon process. The year before, Motorola released results on a 512-bit MRAM. This year's 2.7 to 3.3V chip delivered 35-nsec read speeds and 35-nsec write-cycle times. Motorola's approach employs a per-cell isolation transistor to boost signal strength and consequent read performance, resulting in a 7.1-sq-micron cell ( Figure 3b ). Motorola hopes to bring 32-Mbit or larger, 0.18-micron-based MRAMs to production by 2004, and IBM and partner Infineon have similar ambitions. Infineon is looking at both cells with transistors for DRAM and NOR-flash replacement and transistorless crosspoint cells with slow read performance but, like NAND-flash memory, serially chained for the lowest cost in high-density storage applications. MRAM's advantages over other technologies include the combination of fast reads and writes, nonvolatility, near-infinite cycling capability, full bit alterability, and a simple cell structure. MRAM's developers must overcome additional roadblocks, however, for their hopes to come to fruition. The technology's high write currents, currently approaching 10 mA, may limit array densities if they do not decrease. (Motorola's existing devices program a few bits at a time to minimize write-current draw.) Unintended data alteration by externally applied magnetic fields isn't a significant concern. However, at small process lithographies, cell-to-cell magnetic coupling and consequent data corruption Cost-conscious candidates FRAM replaces the DRAM capacitor's dielectric with ferroelectric material, and one-transistor MRAM replaces the capacitor with a magnetoresistor structure. Why not simply eliminate the capacitor and migrate to an even simpler flash-memory-like one-transistor cell? Hitachi and the University of Cambridge (Cambridge, UK) hope to take this approach with nonvolatile PLEDM (phase-state low-electron-drive memory). PLEDM stacks a small transistor on the gate of a conventional MOSFET and constructs both transistors in a vertical orientation so that they take up no more linear-silicon-die area than a single transistor would require ( Figure 4 ). The main polysilicon gate surrounds the cell; barriers block current flow with the smaller transistor's gate modulating these barriers. Hitachi claims that its integration of one transistor onto the gate of another is a 'first' and that PLEDM-based memories could appear by the middle of this decade. Hitachi and the University of Cambridge aren't content with removal of the cell capacitor, though; they'd like to eliminate the entire transistor. This goal is the premise behind single- or few-electron memories. Once an electron enters and becomes trapped in the quantum-dot region between a gate and a reservoir, the resultant Coulomb forces, being stronger than random or thermal forces, block subsequent electron transfer ( Figure 5a ). In 1993, Hitachi Cambridge Laboratory and the University of Cambridge's Microelectronics Research Center announced the first SEM (single-electron-memory) cell, operating at temperatures close to absolute zero. Subsequent SEM announcements in 1994 and 1995 unveiled room-temperature operation with more conventional silicon-on-insulator materials, and a 1996 announcement discussed a 64-bit array. At the 1997 ISSCC, Hitachi unveiled a functional-room-temperature, 128-Mbit, few-electron memory fabricated on a conventional 0.25-micron CMOS process. Hitachi used 10-nm grain boundaries in polysilicon as its quantum-dot storage traps, and each stored bit represented approximately five trapped electrons. Although five isn't one, it's a lot fewer than the tens of thousands of electrons that most of today's memories need to store a bit. Hitachi's chip used 15V to write, –10V to erase, and 5V to read, and it delivered 20-µsec read speeds. The Hitachi-developed vertical- stacked structure stores 2 bits of information in each memory cell ( Figure 5b ). Another slow-reading-memory technology, 3-D ROM, is even more 'retro' than today's semiconductor memories but with one key advantage: ultralow cost. This brain child of Guobiao Zhang interconnects bit lines and word lines with an amorphous silicon pn-junction diode to define a one; the absence of a diode translates to a zero ( Figure 6a ). Patent filings suggest Matrix Semiconductor is also working on this technology. The inclusion of an antifuse layer between the diode and the word line makes the 3-D-ROM array one-time programmable ( Figure 6b ). Unlike FRAM's ferroelectrics or MRAM's magnetics, amorphous silicon is nonexotic and, thanks to flat-panel displays, a well-understood material whose low temperature deposition and doping don't disturb the underlying IC. A 3-D ROM employs a thin-film, low-current-drive diode to keep bit- and word-line currents at manageable levels, an approach that translates to 0.5- to 5-µsec random per-bit read latencies. Zhang suggests solving the latency problem in two ways: first, by reading a large number of locations within each array in parallel via a wide data bus and then, by stacking multiple arrays atop each other to further widen the bus and lower the array cost ( Figure 6c ). When describing where 3-D ROM might fit in a future multiple-memory-on-system-chip hierarchy, Zhang points to today's multi-discrete-memory hierarchy of fast but expensive SRAM backed by cheaper but slower DRAM and cheapest but slowest hard-disk drive ( Reference 9 ). He believes that on 0.18-micron processes, 3-D ROM costs could approach 5 cents per megabyte. The inability to rewrite 3-D ROM, however, probably means it will find less use than other more flexible mass-storage technologies. Lucent Technologies, which a few years ago introduced plastic-based transistors, continued its cost-reduction mantra with the announcement at last December's IEDM (International Electron Devices Meeting) of an economical flash-memory-like nonvolatile technology. The floating gates of Lucent's storage transistors employ silane-derived nanocrystals as small as 3 nm in diameter instead of the more typical polysilicon. The two approaches deliver comparable cycling endurance and storage lifetimes, but Lucent claims that nanocrystals enable simpler, cheaper, aerosol-based fabrication techniques.
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