In November 1999, when EDN explored general-purpose ASIC/programmable-logic hybrid devices, only Lucent Technologies (soon to be Agere Systems), QuickLogic, and Triscend were shipping products, and Adaptive Silicon and LSI Logic's jointly developed embedded-FPGA test chips were still in design (Reference 1). The FPGAs with embedded-RAM blocks and PLLs that the other vendors kept pointing to as their highly integrated "system chips" didn't count as true hybrids, at least in my book. And those other vendors were vigorously asserting that fully programmable logic chips would sooner or later solve all of your design problems, making hybrids unnecessary (Reference 2).

Fast-forward to the present and look at how things have changed. Lucent, QuickLogic, and Triscend have all broadened their standard-product portfolios. Atmel has joined them, with Altera, Cypress, and Xilinx set to begin shipping their first hybrid chips this year. And, in the embedded-FPGA arena, Adaptive Silicon's past solo status has now become a multivendor race. The competition now includes Systolix; Actel, which last year purchased start-up Prosys Technology; and ICT (Integrated Circuit Technology), which is attempting to reinvent itself as an embedded-PLD-technology provider.

What's changed? Process technology, for one thing. Many vendors surveyed for this article agree that, at the 0.18-micron- lithography threshold, combining the amounts of on-chip ASIC and programmable logic required to begin credibly touting systems on chips becomes cost-effective. A 0.25- or even 0.35-micron process may be sufficient, though, for embedding simple ASIC-housed logic, such as PCI cores or 8-bit microcontrollers. The smaller programmable-logic vendors have all taken advantage of this fact to establish an early lead over today's larger programmable-logic suppliers in the hybrid-standard-product segment, which analysts predict will grow rapidly (Reference 3).

Using the terms "larger" and "smaller" to describe vendors also hints at why the hybrid-chip market has only recently become crowded. Programmable-logic manufacturers have spent years trying to compete against gate-array ASIC suppliers, and to a lesser extent, standard-cell ASIC suppliers. And ASIC manufacturers have focused on beating back the onslaughts of the PLD and FPGA upstarts. Hybrid chips, in some sense, represent both camps' acknowledgment of the alternatives' strengths, along with their own shortcomings. This politically incorrect admission requires a momentum shift in corporate policy that takes longer for larger companies to implement than their smaller, more nimble counterparts. Smaller suppliers also have less to lose and more to gain from the risky midcourse correction that hybrids might represent.

An enhanced FPGA

Traditionally, your system design might have included one or more PLDs or FPGAs containing circuits you design, along with some off-the-shelf RAM, FIFO, and interface-translation chips, and a microcontroller, DSP, CPU, or multiprocessor combination. Now, however, you might want to combine some or all of these functions in one device to eliminate the performance loss, power consumption, and radiated EMI of chip-to-chip interconnect; increase overall reliability; or reduce board space. Still, you don't want to turn your back on the programmable-logic-tool flow that you've already learned and spent lots of money assembling.

Fortunately, you don't have to throw all that design expertise away. The ASIC-housed core appears to your programmable-logic synthesis compiler, and to your fitter or place-and-route tools, as a compiled "black box," with inputs and outputs that you connect to your logic. If you already use the memory-compiler functions offered with FPGAs to construct FIFOs or single- or multiport RAMs, you are familiar with this concept.

For simple or low-flexibility cores, such as PCI, logic and memory in the PLD or FPGA must adapt only minimally (or not at all) to comprehend on-chip IP. You need to specify configuration bits representing variables such as, for PCI, target-versus-initiator function, bus width, I/O-bus and memory-map addresses, vendor and device identifiers, wait states, burst lengths, and the like. This configuration data resides in the programmable-logic partition and fine-tunes the logic that the ASIC gates store. Ironically, nearly the same situation occurs with ASIC-housed complex microcontrollers and microprocessors and their associated "hard" peripherals. Vendors have already designed them; you just need to hook up your logic to them.

The vast middle ground between simple and complex cores requires a more involved approach. As an analogy, recall that some embedded-memory functions use logic or interconnect resources that the programmable logic—not the memory block itself—houses. You might need to construct FIFO status flags, specify a three-state internal bus for bidirectional capability, create a CAM arrangement, or add a register bank to define that the memory operates synchronously. Although you can design this logic yourself, it's often easier and faster to rely on a compiler from a vendor that lets you specify parameters and then automatically creates the configuration for you (Reference 4). The result is a combination of memory arrays plus fixed-location circuits in programmable logic. Their presence leaves fewer logic and routing resources available for the rest of your circuitry.

Now consider, for example, the multiply/accumulators in QuickLogic's QuickDSPs or the multipliers in Xilinx's Virtex-II architecture. For these arithmetic circuits to implement digital-signal-processing functions, you must design a state machine to drive their various control and data inputs and outputs. Again, you could design that state machine yourself, but you might prefer to let the core compiler do the designing for you.

Theoretically, you need only to tell the core compiler that, for example, you'd like to create a fourth-order, lowpass Butterworth filter or, in a more elaborate example, an MP3 decoder. Some of the resulting logic and memory resides in ASIC gates, and the user-customized remainder targets programmable logic. Simplifying this process is at the heart of Xilinx's partnership with The Mathworks. ASIC-housed embedded functions aren't necessarily restricted to purely logic circuits, either. Consider, for example, the high analog content in some of Lucent's hybrid chips, or the ultra-high-speed I/O buffers that both QuickLogic and Xilinx have licensed from Conexant.

Validation variables

Programmable-logic designers have a notorious reputation for following a "blow-and-go" philosophy: Compile the design but don't bother simulating it; stick it into a chip; and, if it doesn't work, scratch your head and repeat the process. That reputation, born in an era of low-density PALs, is becoming increasingly obsolete in the age of multimillion-gate FPGAs, multihundred-macrocell CPLDs and, particularly, programmable-logic/ASIC hybrids. Simulating only the logic you design with test vectors representing how you think the ASIC-housed cores will function is insufficient. You need to functionally simulate the entire chip to comprehend how the hard IP really works and run static timing analyses to ensure the design meets or exceeds target performance (see sidebar "Co-verification choices").

In attempting to balance your desire for in-depth knowledge of the core's operation with vendors' desire to protect their cores from illegal duplication, you'll find that the vendors' simulation models span a range of capabilities and formats (Reference 5). Minimally, you should at least get a bus-functional model, which mimics how the core works but doesn't give away actual circuit-implementation details. The trick, of course, is that the vendor supplying the core must ensure that the simplified model matches the actual core's functions. This task is particularly challenging for complex, superscalar, variable-latency microprocessors, for example. Also, digging into and understanding the circuitry that your logic is interfacing with can sometimes help you debug your circuits.

At the opposite end of the spectrum, some companies quietly provide full RTL HDL models. Expect a thick stack of legal documentation to accompany the code to help ensure that you don't misbehave and either incorporate elements of the core into your designs without license or transfer them to others. As a midpoint alternative, some core developers have turned to either encrypted, secure HDL, such as Cadence's NC-Sim, or precompiled models, such as the Synopsys-championed SmartModels. Xilinx, for example, won't begin shipping samples of its first 0.13-micron PowerPC 405-D5 and Virtex-II-based hybrid chips until late summer, but the company will start sending out development systems by the end of the first quarter, containing SmartModels for the CPU core, CoreConnect bus, and ASIC-housed peripherals.

Altera plans to use the ARM-developed AMBA bus for both its ARM922- and its MIPS32 4Kc-based hybrid-device families, which are built on an Apex 20K programmable-logic foundation. In this case, though, the vendor plans to provide nothing more elaborate than behavioral models for the CPUs and related hard IP. Figure 1's depiction of the devices' architectural block diagram might shed some light on the reasons behind Altera's actions (aside from ARM and MIPS' understandable paranoia about the potential release of their cores' source code into the public domain).

Neither your logic in the programmable-logic partition nor the Altera-supplied soft IP also potentially stored in that partition directly interfaces to the CPU core. Instead, the hookup is through master-and-slave bridges and dual-port SRAM (different from the embedded-array-block memory that the Apex 20K array contains). Altera officials feel that accurately modeled bridges and memory, along with accurate bus-functional models of the remainder of the processor stripe, provide sufficient capability for any presilicon-simulation requirement. Triscend has adopted a similar approach for the interconnect, which the company claims is highly predictable, that links the programmable-logic arrays in Triscend's E5 and A7 devices to the respective 8051 and ARM7TMI cores (Figure 2).

In Triscend's approach, most microprocessor peripherals reside in programmable logic for maximum flexibility. To accurately simulate the chip, you must obtain models not only of the ASIC-housed circuitry but also of the FPGA-based peripherals in the vendor's library. Altera and Xilinx plan a more balanced mix of ASIC- and FPGA-housed peripherals; Atmel's current FPSLIC devices reserve the entire programmable-logic array for your use. QuickLogic isn't yet releasing details of its MIPS32 4Kc- and MIPS64 5Kc-based hybrid chips, which are due out in the second half of this year. Similarly, Lucent Technologies hasn't yet revealed its embedded-processor plans, although the AMBA bus in the company's Orca 4-based hybrids and the company's ARM license are telling clues.

All of the aforementioned hybrid chips, plus most of the others in Table 1, use conventional multiplexer- and LUT-based FPGA structures to implement the programmable logic. One exception is Cypress, which plans to use SRAM-based PLD structures (that is, product-term logic feeding registers) from the Delta 39K for its PSI (Programmable Serial Interface) hybrid chips. These chips place SERDES and SONET, Infiniband, Fibre Channel, or Gigabit Ethernet high-speed interfaces in the ASIC partition. The choice of PLD logic is peculiar, particularly at the several-hundred- to several-thousand-macrocell-count levels that Cypress plans to embed in its PSIs.

Product-term logic is ideal for implementing address decoders and state machines as well as for translating between state machines, data and clock synchronization, handshake protocols and exception handling, control semaphores, and resource management. Register-rich FPGA logic, on the other hand, is ideal for the types of datapath functions you commonly find in the interface-translation applications that Cypress hopes to crack: arithmetic and logic transforms, synchronous pipelines, and similar circuits. And, employing design techniques such as one-hot encoding, you can use FPGA logic to also implement, though sometimes inefficiently, many of the same circuits that PLDs support.

A more flexible ASIC

What if your silicon-design platform of choice isn't programmable logic but standard-cell ASIC? Even the largest FPGA might be too small, too expensive, or too high-power for your needs. Hundred-megahertz processor cores are beyond the capabilities of even hand-tuned FPGA layouts, regardless of what the vendors might be telling you. Or you might require embedded DRAM or mixed-signal capability that off-the-shelf programmable-logic devices don't offer.

All news is not good news with ASICs, though. Mess up your design, and you're potentially staring at hundreds of thousands or even millions of dollars in additional mask-set charges. Throughput from design completion to first silicon back from your ASIC partner takes weeks or months, versus minutes or hours for programmable-logic-based equivalents. ASIC-housed designs aren't amenable to in-the-field upgrades to fix bugs or add features. And you can't easily customize their hardware to enable one silicon platform to service multiple applications.

For these reasons, you might want to add embedded-FPGA capability to your ASIC. And vendors such as Actel, Adaptive Silicon, Atmel, Lucent Technologies, and Systolix are happy to help you do it. The conventional ASIC design-and-validation flow is much more complex than in the previously described standard-product approach targeting FPGAs (Figure 3). The preferred synthesis compiler is an ASIC-optimized product such as Synopsys' Design Compiler. This distinction is important, because this compiler is optimized for the fine-grained ASIC structure, not the coarser programmable-logic cell.

Actel therefore recommends that you obtain and use a separate programmable-logic-optimized synthesis compiler for the portion of your design that goes into its VariCore embedded FPGAs. Actel has chosen for its technology a conventional logic-cell approach, consisting of dual three-input LUTs feeding a register (Figure 4). Reflecting the fact that FPGA compilers are tuned for the more common four-input LUT structure, the Actel logic cell can optionally but less efficiently group the two three-input LUTs into one four-LUT equivalent.

A review of Actel's VariCore data sheet reveals some curious omissions: no hardware multipliers or other arithmetic-optimized structures, no three-state buffers or bidirectional buses, and no partial-reconfiguration capability. The embedded FPGA arrangement does, however, include built-in vertical-carry chains that optionally connect to one of the three LUT inputs. Each FG (functional group) contains four pairs of three-input LUTs and four registers. The registers share common control inputs (enable, preset, reset, and clock).

The next level of hierarchy is the PEG (programmable-embedded-gate) array, an 8´8 matrix of FGs that Actel estimates represents a multiple-design average of 2500 ASIC gates, excluding RAM. (Some FPGA vendors use RAM to artificially boost their system-gate counts (Reference 6).) Actel, along with partners Chartered, TSMC, and UMC, initially plans to offer 2´1, 2´2, 4´2, and 4´4 PEG structures on 0.18-micron process technologies (Table 2). You can orient these multi-PEG arrangements in square, rectangular, and even L-shaped structures.

According to Actel, the ideal VariCore shape is square, which minimizes the internal delays within the FPGA core. However, in some applications, a different-shaped core provides a more efficient implementation at the physical level. Also, each of the PEG blocks with external edges provides 48 inputs and outputs per horizontal edge and 32 inputs and outputs per vertical edge. A 2´2 PEG array offers a maximum of 640 inputs and outputs, whereas a 4´1 equivalent contains 704 inputs and outputs. The place-and-route software is parameterized to support multiple PEG matrix sizes and orientations, thereby not forcing the HDL source code that you develop at the beginning of the design process to explicitly specify the final physical layout.

The architecture arranges both the logic structures and the routing between them in a hierarchical manner. Actel believes that this approach offers flexibility, predictability in timing and logic usage, and faster place-and-route times (see sidebar "Pinout and performance promises"). In fact, the vendor claims that a design with 70% three-LUT usage on a 4´4 PEG FPGA completely compiles on a 500-MHz PC in about nine minutes and that designs routinely and easily use close to 100% of the FGs. Each multi-PEG array also contains JTAG circuitry and a BIST interface (but not a BIST controller). Because of the fixed-silicon cost of this overhead circuitry, Actel doesn't anticipate offering single-PEG arrays, at least at the 0.18-micron process generation. PEG arrays can also include optional cascadable RAM blocks of 9 kbits each with both 9- and 18-bit data-interface options and built-in FIFO flag logic. You might use these RAM structures, for example, as bridges between ASIC and FPGA logic running at different bus widths and clock speeds.

Do the math

Actel's primary competitor at the moment, Adaptive Silicon, has chosen a completely different programmable-logic structure-and-synthesis flow approach. The company uses an ALU-based logic cell whose heritage extends back to the days when some of the company's founders were employed by National Semiconductor and developed the academically interesting, but economically unprofitable, CLay (Configurable Logic Array) and NAPA (National Adaptive Processing Architecture) FPGAs. Other vendors that have attempted to enter the programmable-logic market with arithmetic-logic-tuned devices include:

• Concurrent Logic, funded and second-sourced by National Semiconductor;
• IBM, a Concurrent licensee;
• Pilkington Microelectronics, acquired by Motorola for its quickly canceled ColdFire-based hybrid- product line; and
• Toshiba, another Pilkington licensee and ultimately another nonplayer in the FPGA business.

As you can see, arithmetic-tuned devices don't have a stellar track record. National Semiconductor's architecture became the foundation of Atmel's AT6000 devices, but Atmel has turned to a more conventional LUT structure for the follow-on AT40K product line, the basis of FPSLIC. Adaptive Silicon officials believe, though, that with an architecture tuned by years of silicon and software experimentation, the company now has a winner. The fundamental building block of Adaptive's MSA (multiscale array) is an enhanced 74LS181 4-bit ALU with a modular carry-look-ahead scheme and optional output registering (Figure 5). Four ALUs group to form a Quad Block, connected to other Quad Blocks by signal routing and ALU-control resources, and 16 Quad Blocks form a Hex Block.

Adaptive Silicon estimates that each Hex Block represents an average of 1500 ASIC gates. The company points out that the logic cell can also implement more generic LUT-like functions via both gate- and ALU-level mapping capability. The interface between programmable- and standard-cell partitions comprises a PLC (programmable-logic-core) control structure in the programmable partition (along with an application-circuit interface) and a matching PLC adapter in the ASIC partition. The vendor has 0.18-micron test chips already in-house from initial partner and investor LSI Logic, and chips from TSMC are due back from fabrication next month.

Adaptive Silicon's silicon approach may be unconventional, but the company's design flow is ASIC-designer-friendly (Figure 6). The synthesis tool set for the programmable-logic partitions is the same one you use for standard-cell-targeted logic: Synopsys' Design Compiler or an equivalent. Adaptive Silicon relies on DesignWare libraries that it developed to perform the necessary translation and architectural optimization of VHDL or Verilog source code. The registers in each logic cell, with scan chains throughout the array, aid in silicon verification. Adaptive Silicon and its ASIC partners tailor the PLC adapter for each application, with a soft macro that manages the programming and test interfaces, a five-pin test-access port, and multiplexed test and data I/O signals. The programmable-logic core comprehends full-chip scan BIST to ensure programming integrity, quiescent power testing, and full-speed testing.

Although their silicon and synthesis techniques may differ, Actel and Adaptive Silicon agree on a few things. First off, both companies strive to seamlessly integrate their embedded FPGA partitions into your chip's layout, functional verification, and static-timing-analysis flows, with GDS II floorplanning layout frames, SDF timing models, and the like. Adaptive Silicon supports partner LSI Logic's CoreWare design flow, including the layout-versus-schematic, transistor-level check before tape-out, even though a dynamically configured programmable-logic partition doesn't use many of the available transistors.

Both vendors also stress the full compatibility of their technologies with standard CMOS processes. Adaptive Silicon prefers to employ a five-layer metal process, although a four-layer version is acceptable. Neither vendor wants its embedded FPGA to be the guilty party that makes the chip too expensive. And, although Actel makes aggressive claims about the superior cost- and power-effectiveness of its VariCores over conventional FPGAs (half the die area, and one-third the power consumption), you should carefully analyze whether those assertions apply to your design.

Actel's claims of die-size savings come from the use of three-input LUTs instead of conventional four-input LUTs. The prediction comes true only if your design and compilation tools efficiently map to the three-input LUTs and inefficiently translate to four-input LUTs. Conventional FPGAs also include peripheral logic (I/O buffers, DLLs, or PLLs, among others) that embedded FPGAs don't include. And speaking of I/O buffers, much of the powers savings that embedded FPGAs claim come from the absence of power-hungry I/O buffers in an embedded configuration relying exclusively on on-chip interconnect.

The rest of the pack

Actel and Adaptive Silicon may be today's most visible embedded-programmable-logic advocates, but they aren't the only games in town. Tiny UK IP vendor Systolix, comprising ex-Pilkington employees, recently scored a coup when Analog Devices unveiled the AD7725 16-bit Delta-Sigma ADC containing a Systolix-developed PulseDSP programmable ALU array. The ASIC divisions of both Atmel and Lucent announced their respective embedded-FPGA capabilities months or years ago, although when questioned, neither vendor can provide much tangible information beyond pointing to their hybrid standard products as proof of concept.

PLA vendor ICT hopes to move its programmable AND/OR PAL technology to the world of IP cores. The company points out that the portions of a design most likely to change, such as state machines, control-signal translation, and address decoders, are ideal applications for PLAs. Unlike Cypress, ICT isn't trying to convince customers to embed large chunks of product-term-based logic on their chips. Such an approach would quickly become cost-prohibitive, particularly in a global-routing-matrix structure. Instead, the company wants you to scatter small PLAs across the ASIC.

Like Cypress, however, ICT is moving away from an EEPROM-based technology toward an approach employing SRAM to store configuration-bit values. Embracing SRAM in this manner enables the company to leverage the most advanced processes at multiple ASIC vendors and foundries. ICT, along with partner Faraday, is designing a proof-of-concept hybrid using discrete programmable-logic devices. The first embedded PLA bond-out chips, targeting UMC's 0.15-micron process, are scheduled for tape-out in March.