Soft-start regulator starts at 0V

Gerald L Kmetz, Micrel Semiconductor, San Jose, CA -- EDN, 6/6/1996

Voltage-regulator outputs typically step abruptly at turn-on. Increasing the turn-on interval using some form of slew limiting decreases the surge current seen by both the regulator and system. The circuit in Figure 1a provides soft-start capability for a voltage regulator. Unfortunately, this circuit has three disadvantages: First, the circuit depends on an output voltage to create V_ADJ=V_REF, which means start-up is a step-function pedestal of about 1.2V. Second, placing a reactance in the feedback loop affects the system-transfer function, which can lead to stability or settling-time problems. Finally, the circuit does not recover from a momentary interruption of the input supply voltage, which defeats the soft-start behavior for the second turn-on.

The circuit in Figure 1b overcomes these disadvantages. Unlike simpler approaches, this circuit starts up at an output of 0V. This circuit doesn't add any reactive components to the feedback circuit, which prevents any impact on stability and transient response. The value of R_T should be considerably smaller than that of R₃ to assure that the junction of R_T and C_T acts as a voltage source driving R₃ and to assure that R_T is the primary timing control. If sufficient current flows into the loop summing junction through R₃ to generate V_ADJ>V_REF, then V_OUT is 0V. As RT charges C_T, V_CONTROL decays, which eventually results in V_ADJREF. However, because V_ADJ=V_REF during normal operation, V_OUT becomes greater than 0V. The process continues until V_CONTROL decays to V_REF+0.6V, and V_OUT reaches the desired value.

This circuit requires a regulator with an enable function, because a small (less than 2V) spike occurs when you apply a step-function input voltage. C₁ and R₄ provide the short hold-off time required to eliminate this spike.

Figure 2 illustrates the input and output waveforms for the circuit in Figure 1b. The small initial delay (about 40 msec) is the time interval during which V_ADJ>V_REF. Because V_IN is usually a fairly consistent value, you can choose R₃ to minimize this delay. If you calculate R₃ based on the minimum possible V_IN, then higher values of V_IN produce additional delay before the turn-on ramp begins. Conversely, if you use the maximum V_IN to calculate R₃, lower values of V_IN do not produce the desired turn-on characteristic. In this case, there is a small initial step function before the desired turn-on waveform.

If a momentary interruption of input voltage occurs, D₁ rapidly discharges C_T. The build-up of regulator output voltage is less logarithmic than an R_C charge curve, because only an initial portion of the R_C charge waveform is used (the part for which V_CONTROL>V_REF+0.6V).

The actual time constant in Figure 2 is 0.33 sec, so 3t is 1 sec. As Figure 2 shows, this provides about 400 msec of ramp time (10 to 90%). The whole curve (0 to 100%, or about 600 msec) corresponds to the first 60% of the capacitor RC charge curve.

You can calculate R₃ as follows. At turn-on time, force V_ADJ=1.5V (just slightly higher than V_REF). Then, I_CONTROL=1.5V/[(R₁ X R₂) /(R₁+R₂)] and R₃=(V_IN(MIN)-0.6V)/I_CONTROL. Because IC₁ is a low-dropout regulator, 6V was chosen for V_IN(MIN). This value corresponds to the small (approximately 40 msec) delay before the output begins to rise. With a 7V input, the initial delay is considerably more noticeable. (DI #1875)