News and New Products

Pumped-up EDA-verification tools tackle complex deep-submicron chips

-- EDN, 6/6/1996

 Four companies have recently announced design-verification products. These products reflect the need for tools and techniques for extracting device and interconnect information from deep-submicron chips with millions of transistors and for evaluating these complex designs. Simplex Solutions' Fire & Ice and Thunder & Lightning tools perform full-chip 3-D extraction on 4 million-transistor circuits in 24 hours. Dynamic power verification and signal compliance take another 10 hours per 100 test vectors on the same chip. Fire & Ice, a high-capacity, 3-D IC tool, hierarchically extracts transistor and RC parasitics from a GDS-II layout file. The tool calculates interconnect capacitance, including lumped, coupled and distributed, and resistance to within 5 to 10% that of measured silicon or calculated by Poisson field solvers. Fire & Ice extracts area, lateral, and fringing capacitance in the presence of multiple surrounding bodies, increasing the accuracy of signal-coupling information.

Thunder & Lightning provides power-grid, clock-tree and signal-integrity (SI) verification, performing dynamic analysis of multimillion-transistor chips. The tool uses vectors from a Verilog file to determine active power dissipation. Thunder & Lightning also supplies power-grid verification, including IR drop for supply-voltage degradation and current density for potential electromigration or power/ground-bounce problems. With Fire & Ice, Thunder & Lightning checks signal clock-skew compliance, coupling noise, and reliability analysis. Compliance testing includes rise and fall slew rates, signal glitches, setup-and-hold violations, and other SI problems. The integrated tool signal- and power-compliance suite, available in July, runs on Hewlett-Packard and Sun workstations and will be available on IBM platforms in the third quarter. Prices start at $150,000.

Avanti announced a trio of tools, including Star, a deep-submicron-analysis tool. The tool does full-chip extraction, delay calculation and data reduction during physical design. Star integrates with ArcCell and Vericheck, Avanti's hierarchical layout-and-verification tools. Star's Smart Extraction extracts transistors and RC-wiring parasitics for an entire chip. According to Avanti, the Smart Extraction capability automatically determines and applies the correct level of extraction accuracy for each net in a chip. Star supports GDS-II and Caltech Intermediate Format input and outputs Spice and Standard Parasitic Format (SPF) circuit netlists and Standard Delay Format (SDF) for delay information. For delay calculation, the tool supports k-factor and table models as well as models in Pearl, Synopsys, and Verilog tools. Star with extraction, data reduction, delay calculation, and a technology CAD (TCAD) interface is available now on Digital Equipment, Hewlett-Packard, IBM, Silicon Graphics, and Sun platforms. Prices start at $125,000. A graphical delay-analysis tool will be available in the third quarter.

Mentor's Calibre, a set of chip-verification tools, is available in different configurations. You use some configurations for flat designs, such as standard cell chips, and others for hierarchical designs, for more complex chips. Versions of the tool are also available for multiple processor verification of very large designs. To accelerate verification time, the hierarchical variants employ a "hierarchical-injection" technique. Calibre uses this technique to analyze interactions between hierarchical levels of the design and creates additional cell groupings that recognize common structures. Calibre then makes a "superhierarchy" of the design that improves tool runtime efficiency by examining repeated patterns only once, even if they span hierarchical design levels, instead of at each occurrence of a cell. This technique improves physical-design verification, regardless of the way you've done the hierarchical-design implementation. All configurations of Calibre use the Standard Verification Rule Format (SVRF) standard. The product line runs on Digital Equipment, Hewlett-Packard, and Sun platforms. Calibre includes DRC for design-rule checking ($40,000); LVS for layout-vs-schematic comparison ($40,000); and H-DRC and H-LVS ($75,000 each), both of which include hierarchical-injection capability; and multiprocessor DRC (starting at $50,000), which lets you run problems concurrently on multiple machines. All Calibre tools are available now, except for H-LVS, which will become available in August.

Frequency Technology targets its Accurate True 3D Calibration service at making interconnect extraction tools more efficient at sub-half-micron levels. Frequency tunes and calibrates extraction tools, eliminating unnecessary design guard-banding used to account for chip-interconnect parasitics. The service includes evaluating and validating extraction tools on a rule-by-rule basis; determining accurate process parameters, if required; calculating an appropriate guard-band scheme and optimizing rule files for extracting and calculating delay; and evaluating guard-band impact on design performance. Frequency's service is available now; the company prices the service on a case-by-case basis.

—by Jim Lipman

Simplex Solutions, San Jose, CA. (408) 432-8260, fax (408) 432-8262.

Avanti, Sunnyvale, CA. (408) 738-8881, fax (408) 738-8508, http://www.avanticorp.com

Mentor Graphics, Wilsonville, OR. (503) 685-7000, fax (503) 685-1212, http://www.mentorg.com .

Frequency Technology, Los Altos, CA. (415) 917-5800, fax (415) 917-5817.