Feature

Programmable logic: Beat the heat on power consumption

Higher performanceand gate countsincrease programmable-logic powerconsumption. Wise device selection and design techniques can significantly improve your chances of coming in under the powerbudget.

By Brian Dipert, Technical Editor -- EDN, 8/1/1997

Power consumption, long a concern in ASIC designs, is becoming an issue in programmable logic--at much lower gate counts. The more power a chip uses, the hotter it operates and the slower it runs. Excessive power can be a concern in battery-operated designs, designs with interface cards, and closed-box designs with poor heat dissipation or systems without fans.

Even if your design lacks these characteristics, other practical reasons exist to concern yourself with power consumption. For example, device reliability also rapidly decreases at higher temperatures (see box "Measuring temperature the all-natural way"). For this reason, semiconductor vendors use high temperatures to accelerate potential failure mechanisms when characterizing new processes. And, because gate count is one key determinant of power consumption, power restrictions may impact the amount of logic you can integrate onto a device. Power consumption also closely ties to signal toggle frequencies, so power improvements also tend to reduce EMI and other noise effects.

Designs typically use coarse-grained PLD and FPGA logic blocks less efficiently than the ASIC NAND gate architecture, thus wasting logic. Also, routing resources in PLDs and FPGAs are less abundant and direct and have higher intrinsic impedance than their ASIC counterparts, negatively impacting power. Although you cannot precisely predict power consumption, educated decisions in device selection and design techniques can significantly improve your chances of coming in under the power budget. Many of these design techniques require trade-offs in performance and other key factors, however.

How hot is too hot?

Data sheets and packaging guides provide several specifications for determining a device's maximum power consumption. These specifications include

• T_J, or maximum allowed junction temperature of the silicon in degrees Celsius,

• T_A, or allowed ambient temperature range in degrees Celsius, and

• uppercase theta_JA, or junction-to-ambient thermal resistance of the device/package combination in degrees Celsius per watt.

Vendors often specify junction-to-ambient thermal resistance at several levels of forced airflow in feet per second. The spec also varies with package size, with larger usually being better; architecture: QFP vs BGA, for example; die orientation: whether the active-circuit side of the die is up or down; and material: ceramic vs plastic.

After determining your system's worst-case ambient temperature, use the following equation to calculate the maximum allowable device power consumption in the selected package:

where P_MAX is the maximum allowable device power consumption.

If the package includes a heat sink, you should also calculate P_MAX using the vendor-supplied uppercase theta_JC (junction-to- case thermal resistance), uppercase theta_CA (case-to-ambient thermal resistance), and T_C (maximum allowed case temperature) values and equation:

Use the lower value of P_MAX as your design target.

Although a vendor may specify a device as functional as high as the maximum allowed junction temperature, closely read the data sheet to determine whether the specifications derate above a lower temperature. For example, some vendors guarantee plastic-packaged programmable-logic devices to operate at a maximum allowed junction temperature of 125°C, but performance degrades beyond 85°C.

Also, look at the device's reliability report and determine the mean time between failures or the number of failures in a given time at the maximum junction temperature. If the failures in time or mean time between failures do not meet your system lifetime expectations, you must reduce power or choose another device or package.

Low voltage: the quick fix

The most straightforward method to reduce power consumption is to lower the chip's operating voltage, as the following equations show. For static-power consumption,

For dynamic-power consumption,

These calculations apply both to the internal-device power consumption and to the incremental power draw that the I/O buffers and interconnect between devices cause. In both static and dynamic cases, power varies with the square of the voltage. When you convert your design from a nominal 5V to a 3.3V operating voltage, for example, you theoretically decrease power almost 60%. Smaller differentials between one and zero on device outputs also mean lower power burn.

The first low-voltage programmable-logic parts were screened chips built on a 5V semiconductor process. These devices had several shortcomings. First, vendors did not produce these devices on a process specifically for low voltages or design them with low-voltage-specialized circuits. This fact means that the devices ran slower than their 5V counterparts, outputs had lower drive capability, and yields were low, keeping costs--and, therefore, prices--high. Also, their inputs weren't 5V-tolerant, cluttering the interface with bus-voltage converters or serial voltage-drop resistors.

These approaches limited board space, cost, performance, power, and reliability. Forward-biasing the input-protection diode also caused unwanted current flow. Further, the devices' output buffer voltage was the same as the supply voltage. As a result, they couldn't interface to other devices' 5V CMOS inputs without voltage translators or open-drain converters and pullup resistors. Again, these approaches were unattractive in many situations. Even if the 5V device had TTL-compatible inputs, the 3.3V program-mable-logic chips could not drive them to the 5V "rail." This inability resulted in higher input leakage current and, therefore, higher system power consumption.

Fast forward to today, and the situation has changed for the better in many instances (Table 1, see pg 76). Vendors are now shipping parts built on low-voltage-optimized processes, solving the performance and yield problems. Power is only one of the reasons that this trend has occurred. Companies are quickly migrating to 0.5-µm and smaller lithographies to boost yields, lower prices, increase performance, and raise the number of gates that can cost-effectively fit onto a device (Figure 1). Most transistors built on these smaller lithographies, however, suffer from "punch-through," meaning that they cannot tolerate 5V. This phenomenon causes breakdown of the transistor-gate oxide. Like their DRAM and CPU counterparts, PLD and FPGA companies are moving--some faster than others--down a voltage "staircase." Atmel's ATF1500ABV and AT6000LV, ICT's PEEL22LV10AZP, and Waferscale Integration's ZPSD4xxV and ZPSD5xxV product families operate as low as 2.7V, and many vendors supply chips that operate at 3 to 3.6V.

Many companies claim that their devices' inputs are 5V-tolerant even at lower operating voltages. But make sure that you carefully read the assumptions. In some cases, vendors guarantee reliable operation only when the interfacing chips operate at or below a maximum voltage differential. A 5V device operating at the upper end of its operating-voltage range and interfacing to a 3.3V device operating at the low end of its range could cause problems. Vendors might also require a power-up sequence between devices that your design can't tolerate. You may also still be slightly forward-biasing the input-protection diode, thus burning power. Also, closely analyze a vendor's claims, for example, that its 3.3V parts can directly interface to 5V inputs. This claim sometimes means that the parts can drive valid 5V TTL states but not full CMOS levels.

An even better approach is isolating the supply and I/O voltages from each other within the chip so that the core can run at one voltage while the I/O ring operates at another (Table 1). Better yet, the ability to run individual I/O pins at either the supply or the I/O voltage gives maximum flexibility. Motorola's MPA1000 FPGA family and products from Gatefield provide this capability.

A design can achieve lowest power when operating at the lower end of an allowable voltage range. However, ensure that momentary voltage droops (caused by turning on additional circuits) or glitches (caused by fast-switching device outputs) don't cause the supply voltage to transition below the specified minimum. Another advantage of splitting supply and I/O voltages is that it isolates the core from output-transition noise.

At this year's IEEE Custom Integrated Circuits Conference in Santa Clara, CA, in May, Altera described a future product feature, the voltage-supply converter (VSC) (Reference 1). VSC allows the supply-voltage input to remain at a constant voltage, such as 5V, regardless of the true internal core voltage and, therefore, helps isolate your design from external-supply voltage conversions caused by process steppings. Altera admits, however, that the VSC circuits add approximately 2% to the die area of the 50,000-gate "typical" EPF10K50V development chip. Traditionally, voltage converters also are not 100% power-efficient.

Define internal dynamic power

Besides voltage, frequency and capacitance are the other parameters of the dynamic-power-consumption equation. For internal power consumption (that is, consumption other than that caused by device inputs and outputs), the main objectives for reducing dynamic power include decreasing the average logic-switching frequency; reducing the amount of logic switching at each clock edge; and lowering the capacitance of the routing network, especially for high frequency signals. For full-CMOS devices, dynamic consumption primarily determines overall device power usage, so time spent in this area reaps significant rewards. First, make sure that your compiler automatically disables unused logic.

A CMOS logic gate, such as a simple inverter, with P- and N-type transistors for pullup and pulldown functions, respectively, ideally consumes power only when switching (Figure 2). This situation results from the fact that these transistors create a momentary power-to-ground current path during logic transitions when both transistors are partially on. Without fundamentally changing your design, you can significantly improve power consumption by reducing or eliminating unnecessary logic transitions. For example, control skew between logic-gate inputs. Ensure that flip-flop inputs meet setup-and-hold-time requirements to avoid extended output settling transitions caused by metastability (Reference 2). Run high-frequency signals through as few intermediate logic levels as possible. Eliminate pipelined stages as long as doing so doesn't adversely impact performance. And, use only as many flip-flops as you need to store data values; for example, use a 3-bit instead of a 32-bit register to store numbers that vary only from +2 to ­2.

One often-forgotten yet effective technique is gating off

inputs as they enter the chip. For example, in an address-decoder circuit, even

if you deselect the target device, signals shared with other peripherals, such

as addresses coming from a host CPU, toggle, reflecting other bus activity (Figure 3). Gating these addresses with a select line, although it may result in a more complex circuit, keeps unwanted transitions from propagating throughout the remainder of the device's logic.

Careful state-machine selection can also help reduce power.

Gray coding is a design technique in which only one logic output changes each

clock edge. Compared with a more traditional binary counter that uses all

available values as valid states, a fully gray-coded state machine can require

more flip-flops. However, gray-coding only the most common state transitions

reduces or eliminates the need for additional flip-flops and reduces the average

number of logic transitions per clock (Figure 4). Focus your gray-coding efforts on common return-to-zero state transitions. You can use the same techniques for other counter applications, such as internal-memory addressing.

One-hot linear-feedback shift-register (LFSR)- and other shift-register-based state machines contain a large number of flip-flops. An LFSR also has a high average number of flip-flops toggling states with each clock edge. Carefully select an appropriate arithmetic circuit. Carry-look-ahead logic can produce faster results than can its generic ripple-carry counterpart but typically also at much higher comparative power consumption. By using a chip's dedicated ripple-carry routing, you can sometimes produce results as fast as or faster than and with lower operating power than carry-look-ahead alternatives.

Clock frequency primarily determines dynamic-power consumption for synchronous circuits. Many PLDs and all FPGAs enable you to drive each flip-flop or group of flip-flops from one of several clock inputs. Many devices also let you use a generic input as the flip-flop clock but usually at the trade-offs of increased skew and input setup-and-hold-time requirements. When driving portions of a chip's logic at different clock frequencies, the clocks should ideally be multiples of each other, and skew between their corresponding rising and falling edges should be minimal. If the logic circuits interact with each other and you don't follow these guidelines, your design could end up with metastability. The safest approach may be to route one master clock into the chip, dividing it into subclocks once inside.

Once you selectively drive circuits with appropriate clocks, the next step in reducing overall power draw is to slow or stop a clock when possible. You can most easily implement this technique in infrequently used circuits, such as arithmetic functions and memory. You can selectively and, therefore, quickly in-system-reconfigure the PLLs in Lucent Technologies' upcoming ORCA 3C and 3T product families. When you use the PLL as an on-chip clock multiplier, you can redefine it to slow the multiplied clock when circuits are not in use. (This approach is similar to the one that low-power CPUs use.) This technique usually has a low-end frequency limit, though, below which the PLL tends to lose its "lock."

If you want to stop the clock, you can either suspend the external oscillator or gate the clock as it enters the chip. In either case, ensure that the chosen circuit allows no possibility for glitches, and research the programmable-logic device's recovery behavior after clock suspension. Alternatively, you could use an FPGA having flip-flops with dedicated clock enables. Although they don't reduce the power consumption of driving the clock down routing lines, enables can reduce or eliminate power that each flip-flop consumes.

One clock-enable approach simply multiplexes between the normal D-type flip-flop input and its previous output. This technique eliminates the possibility of glitches, but a portion of the flip-flop circuit still responds to rising and falling clock edges. The alternative approach, gating the clock, means that no portion of the flip-flop circuit burns power, but you must be careful that race conditions between the clock and enable don't cause unwanted toggles. Regardless of implementation, dedicated clock enables don't force you to use up generic-logic decoding resources to accomplish the equivalent function. Dedicated enables also are more predictable in operation than generic-logic equivalents. However, you might encounter granularity problems if a logic block contains multiple flip-flops because they usually share an enable signal. (The same restriction applies to sets and resets.)

Because routing resources, being nonideal, have a measurable capacitance, the dynamic-power-consumption equation also applies to them. Capacitance is a function of inherent route characteristics (length, width, and impe dance) and the number of distributed loads (flip-flops, logic gates, and routing segment interconnects). A long routing typically has higher capacitance than its shorter alternative if the routing requirement is minimal, that is, if logic blocks are close to each other on the die. On the other hand, if the signal routing requirement is long, a discrete long line provides lower capacitance than a series of shorter segments, which you must "stitch" together with pass transistors or antifuse links. When comparing their devices' power consumption to competitors' products, vendors with architectures in which long routing lines dominate assume that designs require them. Vendors with architectures in which short routing lines dominate assume that designs require them. Because the truth is probably somewhere in between, some vendors offer a variety of routing resources on a device.

Also, dynamic-power consumption increases at higher frequencies and switching speeds. If your programmable-logic device offers various routing lengths and internal signal-buffer strengths, choose only what you need for your performance targets to avoid burning unnecessary power. Choose a strong-enough buffer, however: Not enough strength both decreases speed and increases the amount of time that logic gates remain in their high-power switching state. In addition to variable-length generic routing lines, many FPGAs offer optional dedicated routing paths for common clock, carry-in/carry-out, and other signals. It's tempting to take advantage of these resources, because they can significantly improve a circuit's performance. However, dedicated long-line and heavily loaded routes can also mean higher power consumption. Estimate both power and performance before you decide.

Programmable-logic companies focus on improving the capability and flexibility of each logic block to minimize the need for power- and speed-consuming block-to-block routing. Lucent Technologies and Xilinx also plan to offer dedicated interlogic-block-signal feedback in their upcoming FPGA architectures. The more efficiently you use the available resources in each logic element, the less generic routing you need and the less power you burn. Manual floorplanning can aid automated place-and-route tools in optimizing your design.

In addition, watch out for transient short circuits on internal buses. Besides being a long-term reliability concern, they cause the chip to draw excessive current. Three-state buses are the common culprit here: One buffer begins to drive the interconnect before another has finished. If your design comprises a series of outputs selectively driving one input, consider a multiplexer configuration. Although it may require more gates than a three-state buffer, a multiplexer eliminates the possibility of bus contention. Three-state buses also often require internal pullup resistors and higher current signal drivers.

Output transistors, regardless of loading, are subject to the same momentary power-to-ground short circuits as internal-logic gates. This situation multiplies the impact to device power consumption, because outputs source and sink higher current than their internal counterparts. If a programmable-logic device provides multiple output-drive or slew-rate options, choose only what you need to meet performance targets. However, choosing too small a buffer or too low a slew rate keeps other devices' inputs in their highest power transitional state for an extended time.

You can typically reduce chip-to-chip interconnect dynamic power by limiting the number of I/O pins, the loading on each pin, and the average frequency at which each pin toggles. Minimizing trace lengths between a programmable-logic chip's output and other devices' inputs limits interconnection capacitance and dynamic-power consumption. You can also reduce power draw by tristating outputs when not using them. PLDs have various numbers of dedicated output enables, and some even let you use generic device inputs for this function. Ensure that other devices drive PLD and FPGA inputs with fast-enough slew rates to minimize switching time--but not so fast that they create unwanted system noise.

Just as with internal gates, extraneous glitches on device inputs or outputs burn power. Some devices offer a "bus-keeper" capability to weakly hold chip outputs at their previous value when three-stated or when the chip enters power-down mode in the absence of another device's driving the bus. Integrate as many functions on one chip as you can without exceeding the device's thermal rating. For example, some of Altera's and Lattice's CPLDs and many FPGAs let you synthesize memory bits on chip using available RAM and logic-gate resources. If your de-sign's density needs are small enough, on-chip memory can offer higher performance and lower power than its off-chip equivalent.

Static power

Almost all FPGAs are full-CMOS devices and, therefore, consume little current in a static state, meaning that no inputs or outputs are changing and no internal logic is toggling. Their static-power draw comes from various sources, including nonideal and not fully on or off I/O and internal transistors as well as resistance of routing interconnections. Other sources include internal pullup and pulldown resistors on inputs and three-state drivers; device outputs driving resistive loads, such as pullup and pulldown resistors and bipolar transistors; and the circuitry necessary to program and retain the configuration of look-up tables, multiplexers, and pass transistors.

Besides these factors, many PLDs contain internal analog

sense amplifiers. Each row of the PLD logic array drives an optional macrocell

flip-flop (Figure 5a). The main advantage of this approach is speed. However, each unasserted product term--and, depending on the logic complexity, odds are that there are many such terms in each row--provides a constant-current path from the supply voltage to ground, thanks to the "on" transistor.

PLDs with low-power options (sometimes called "quarter-power" because they consume approximately one-quarter the current of first-generation bipolar parts) often "detune," or reduce, the sense-amp strength, alter the resistor size, and use other techniques to reduce current draw. However, in exchange, they run slower than their full-power counterparts. For increased design flexibility, some devices let you configure low power or high performance on a smaller-than-entire-device level (Table 1). This granularity can be per-logic block (group of macrocells) or even per-macrocell. Vantis offers a choice of four power levels on its MACH5 family.

Another approach, static-power-down mode, or "zero-power," uses input-transition-detection circuitry. In this approach, when device inputs don't change for a time--ty pically, several tens of nanoseconds--the part automatically powers down the sense amps, considerably reducing current draw. Many low-power nonvolatile and volatile memories use similar techniques. Recovery from power-down is noninstantaneous, however, leading to a longer input-to-output propagation delay. Because you can't directly control or know when the PLD is in normal or power-down mode, timing specifications typically include the recovery time. Waferscale Integration's ZPSD product lines extend automatic-power-down techniques beyond the generic-logic array to dedicated-logic functions, such as chip decoding and timers/counters, and to on-chip RAM and ROM. The company also uses differential logic and sensing to limit the required internal voltage swing and, therefore, reduce dynamic-power consumption.

Systems with high performance requirements can have a problem with the extended propagation delay that automatic power-down causes. The timing is also unpredictable, depending on whether the chip is already "awake" when its inputs change. This problem should be of no concern in properly designed synchronous circuits but can cause race conditions and subsequent signal glitches in multichip, asynchronous designs. As an alternative, some vendors offer a dedicated power-down input-pin option. With power-down inactive, the chip runs at full speed, and when you drive the power-down pin active, the chip goes into sleep mode. Data sheets for these parts document the wake-up time.

Because today's submicron logic gates provide faster

propagation than their larger, older counterparts, Philips uses an all-CMOS

architecture for its re-entry into the PLD market. The Philips approach uses a

series of CMOS gates to decode the desired logic function (Figure 5b). Although CoolRunner devices run a few nanoseconds slower than the fastest specified alternatives from other companies, they offer lower power consumption in both active and, especially, standby modes with no wake-up latencies when exiting standby and no power-down pins.

Even if a device has TTL-compatible inputs, you should try to drive them to full-CMOS levels. If both interfacing chips are CMOS-based and run at the same I/O voltage, this goal shouldn't be difficult to achieve. However, this scenario can be a problem when you are attempting to directly drive a 5V TTL-compatible input with a 3.3V output. Avoid driving resistive loads, such as pullup and pulldown resistors and bipolar transistors. For lowest power consumption, also avoid using the internal pullup resistors and pulldown resistors in many PLDs and FPGAs to configure unused device inputs. Instead, you can tie the inputs to an external V_CC or ground. This approach makes your board design less flexible to last-minute design changes, however (Reference 3). Alternatively, the "MAKEBITS-TIE" option in Xilinx's compiler automatically connects unused inputs to other inputs or outputs. You must ensure that the option chooses low-frequency signals. Some devices also use the bus-keeper feature to control unused inputs via internal latches instead of resistors.

To increase power-down time for sense-amp-based PLDs, consider using a clock with an asymmetrical duty cycle. If, for example, your design operates at 10 MHz and your PLD enters power-down mode after 50 nsec of input inactivity, a clock with 20 nsec of "high" time and 80 nsec of "low" time uses less power than its 50%-duty-cycle alternative. Also, watch out for spurious glitches on device inputs; each transition wakes up the part. Chips with input-transition detection are also sensitive to slew rate: If you too slowly ramp an input up or down, the part might not see the transition and not wake up.

Need more ideas?

If you need other options for handling heat, evaluate packages. Ceramic, although more expensive than plastic, provides better heat dissipation. A larger package with more surface area also often offers better thermal characteristics. Newer array packages, such as BGAs and PGAs, have lower bond -wire and lead-frame capacitance than do peripheral alternatives, such as QFPs and PLCCs. Some packages include internal heat sinks, or "spreaders." Packages with die-down orientations also typically have better thermal ratings than die-up options. Vendors specify packages' thermal ratings at various airflow rates; adding or rerouting a system fan can significantly affect results. In a worst-case scenario, you can add a heat sink or dedicated fan, although these options may not meet your component height, footprint, or cost targets.

Resource sharing, a technique compilers commonly use to reduce gate count, can deliver unpredictable power results. On the one hand, it produces less logic. On the other hand, these shared gates toggle more frequently, contain additional control inputs to define their functions, and have more heavily loaded outputs. Results are equally unpredictable if you replace a faster and narrower circuit with its wider but slower alternative. For example, what happens if you use a 16-bit, 25-MHz comparator instead of an 8-bit, 50-MHz one? The design uses more gates, but they run half as fast. Evaluate this approach especially if the slower logic would let a sense-amp-based PLD enter its low-power mode.

Although many engineers refuse to consider another alternative, asynchronous-logic design, its lack of a clock can considerably reduce power consumption compared with a synchronous alternative in a complex design. Keep in mind, though, that designing a circuit, such as a ripple counter, that appropriately responds to all possible sequences and timing variations between device inputs is challenging, and this circuit will probably require a redesign if you move it to a future product, process step, or ASIC.

Another somewhat-esoteric ap-proach is reconfigurable computing, in which you dynamically in-system-redefine a generic set of logic, usually in an SRAM-based device, to implement multiple functions. Although you effectively reduce the number of gates necessary to implement a set of tasks, reconfiguration is a relatively high-power operation. Also, SRAM-based FPGAs usually burn more dynamic power than do antifuse-based alternatives because of the capacitance differences between antifuse links and pass transistors. Consider this approach if the reconfiguration occurs infrequently and with FPGA architectures that support partial reconfiguration, such as Atmel's AT6000 and Xilinx's XC6200 product families.

Why not just power off the chip when you're not using it? Although this "brute-force" approach certainly minimizes power consumption, it may cause more problems than it solves. It requires that you run split power supplies to portions of the board or use a beefy external FET for localized voltage switching. Carefully characterize a device's power-up and -down behavior, especially in the presence of active clocks and other inputs. You also must reconfigure SRAM-based FPGAs whenever you restart them. Finally, electrically isolate the chip from the rest of the system so that it does not try to power itself from the interconnection to other devices in lieu of an active V_CC supply; the chip will probably destroy those devices in the process.

Ultimately, you may have to partition your design among multiple chips. This approach usually results in higher system power consumption but may get you under the power limit for each device. Intelligently partition functions to minimize interaction between chips, which burns interconnect power.

Says Steven Knapp, a design engineer at OptiMagic, "I/Os can be the biggest single power user on the device. A bad partition can dramatically increase your power consumption." Also, use the opportunity to tune your device selections to the function's needs, such as a slow but power-thrifty FPGA for a big, low-frequency datapath circuit, and a fast PLD for a smaller, high-frequency system state machine.

Predicting results

How do you know how much power your design will consume before plugging the chip into your board and hanging a current meter on it? Unfortunately, you usually can't--at least not with high precision--because the "tools" for programmable logic are less than ideal. However, this situation will probably improve over the next few years. Almost every programmable-logic vendor provides a documented set of equations for calculating static and dynamic power. The more complex the device, the more complex these calculations become. For a small SPLD, for example, sense-amp current dominates static power, and output-buffer transitions dominate dynamic power. Compare this situation with that of a high-end FPGA, which has several levels of internal routing resources, a variety of internal and output-signal buffer strengths, and a multitude of logic-block configurations. Atmel provides a power-estimation output in its macro-builder utility. The estimation essentially provides a graphical representation of the equations, and you can optimize for power consumption, area, and performance with the company's Integrated Design System tool set.

To help you with the calculations, compilers often output the number and type of logic and routing resources your design uses. You know a circuit's clock frequencies, and the vendor also provides multiplicative constants for the power translation. But the remaining--and most difficult to determine--variable is the average number of flip-flops and routing nodes that transition during each clock edge. Determining this value is especially tough for HDL-based designs, in which you have little or no insight into the logic implementation in a chosen device. Some vendors suggest you use a 12.5%-usage estimate, corresponding to the average toggle percentage of a 16-bit counter. Others believe that a 25% estimate for an 8-bit counter is more typical, although you often find them quoting this figure when positioning themselves against perceived higher power competitors. Some circuits, such as arithmetic units and LFSRs, have even higher toggle percentages. Your choice can radically impact the accuracy of your estimation, so when in doubt, aim high.

In determining buffer and routing power, differentiate between a clock and any other signal. Clocks toggle edges twice each period, and each edge charges or discharges capacitance, burning power. A 20-MHz clock provides 40 million transitions/sec. In contrast, other signal flip-flops typically toggle on either the rising or the falling clock edge but not on both. (However, Vantis offers a biphase-clock option in the MACH5 family.)

Concern yourself with not only the overall device power consumption but also the power draw and resultant heat output of specific logic circuits within the chip. Packages offer varying degrees of success in handling thermal stresses from "hot spots" on the die. If your design contains several high-frequency circuits, spread them over the chip. With PLDs, you can often force such a partitioning by carefully selecting I/O pins. With FPGAs, use floorplanning tools to guide mapping, placing, and routing.

---

References

1. Patel, Rakesh, et al, "A 3.3-V programmable logic device that addresses low power supply and interface trends," IEEE Custom Integrated Circuits Conference, May 8, 1997, pg 539.

2. Grosse, Debora, "Keep metastability from killing your digital design," EDN, June 23, 1994, pg 109.

3. Ganssle, Jack, "Resistors in digital circuits," EDN, Feb 2, 1995, pg 169.

4. Cuy, Kenneth M, "Design considerations bring unity to a mixed-voltage world," EDN, Feb 2, 1995, pg 115.

5. Lytle, Craig, "Managing power in high-speed PLDs," EDN, Sept 1, 1995, pg 135.

6. Lipman, Jim, "EDA tools let you track and control CMOS power dissipation," EDN, Nov 23, 1995, pg 65.

7. Dipert, Brian, "Shattering the programmable-logic speed barrier," EDN, May 22, 1997, pg 36.

8. Frenkil, Jerry, "Low-power ASIC design," Integrated System Design, March 1997, pg 40.

9. Birkner, John, "Lowering programmable logic's power consumption," Computer Design/Portable Design Supplement, April 1997, pg 19.

10. Frenkil, Jerry, "Controlling power dissipation in submicron ICs," Computer Design/Portable Design Supplement, April 1997, pg 26.

---

Acknowledgments

Special thanks go to several people for their suggestions and feedback: Ray Andraka from the Andraka Consulting Group, www.ids.net/~randraka; independent consultant Brad Fawcett, bradley@sc.scruznet.com; Jerry Frenkil from Senté, www.powereda.com; Debora Grosse from Agate Technology, dgrosse@pobox.com; Steven Knapp from OptiMagic Logic Design Solutions, www.optimagic.com; and Doug Smith from VeriBest, www.veribest.com.

---

For more information...
When you contact any of the following manufacturers directly, please let them know you read about their products on EDN's website.
Actel Corp Sunnyvale, CA 1-408-739-1010 fax 1-408-739-1540 www.actel.com	Altera Corp San Jose, CA 1-408-894-7000 fax 1-408-435-1394 www.altera.com	AMD Corp Sunnyvale, CA 1-408-732-2400 fax 1-408-749-3240 www.amd.com
Atmel Corp San Jose, CA 1-408-441-0311 fax 1-408-436-4300 www.atmel.com	Cypress Semiconductor San Jose, CA 1-408-943-2600 fax 1-408-943-2741 www.cypress.com	Gatefield Fremont, CA 1-510-623-4400 fax 1-510-226-0147