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Feature
Hot 100 Products 2000
Thousands of new electronic products come along every year. All, no doubt, are useful, and many are innovative, yet only a relative few generate real excitement. At EDN, we've noted that our readers respond in a really big way to about a hundred new products each year. Thus was born, in 1993, a year-end feature, the EDN Hot 100 Products. This year, we present our eighth annual installment.
By Staff -- EDN, 12/7/2000
EDN's Hot 100 Products of 2000 are exciting, and it's an honor for a product to make the list. Our purpose, though, isn't to bestow honors but to report on the year's accomplishments and show the current state of the art. In our fast-moving world, products that made last year's Hot 100 already look quaint, and this year's products will probably look dated a year from now. Right now, though, the Hot 100 Products of 2000 show you where we're going. So don't lose your way. Take a look.
- Communications
- Digital ICs
- Embedded-development tools
- Computers, boards, and buses
- Test & measurement
- Components, hardware, and interconnect
- Software
- EDA tools
- Processors
- Analog ICs and discretes
- Peripherals
- Power sources/controllers
- Multimedia functions
| Chip set provides terabit switching. PMC-Sierra's Tiny Tera One (TT1) switching-fabric, four-chip set features the Line Card to Switch (LCS) Protocol. The protocol supports scalable terabit routers, ATM switches, and optical switches that can transfer tens of gigabits to tens of terabits per second aggregate bandwidth. The fabric supports line cards with both circuit-switched and packet-switched data traffic, such as IP, Packet-Over-SONET, ATM, and frame relay at rates as high as 10 Gbps or 4´2.5 Gbps. The LCS Protocol allows for physical separation between the switching fabric and the line-card racks, supporting in-service switching-fabric upgrades that enable systems to scale up while retaining existing line-card racks. You can configure the TT1 chip set in increments of 10 Gbps per port to a 32-port maximum. The chip set comprises the PM9311/TT1 scheduler, which comes in a 1088-pin flip-chip CCGA and costs $3963; the PM9312/TT1 crossbar in a 1088-pin flip-chip CCGA costing $1693; the PM9313/TT1 data slice in a 474-pin flip-chip CBGA costing $384; and the PM9315 enhanced-port processor in a 624-pin flip-chip CBGA for $880. A chip is worth 240 voices. The VX-SP1000 voice-signal processor from VxTel targets carrier-class switches in next-generation packet networks (Picture). The device can process as many as 240 G.711 uncompressed channels or 120 G.729A compressed channels, each with 64-msec-tail-length echo cancellation and supporting telephony functions, such as comfort-noise generation, voice-activity detection, and dual-tone-multifrequency tone detection and generation. The VX-SP1000 uses four DSP cores for voice, fax, and other broadband-processing algorithms and integrates a µlaw/A-law PCM-highway interface with 512 full-duplex, independent, time-division-multiplexed channels. Additional on-chip resources include the 32-bit VX-bus expansion-bus interface), 8 Mbits of memory, and JTAG/enhanced-JTAG test ports. I/O voltages are 3.3V, and core inputs are 1.8V. 10-Gibabit Ethernet switchers target optical networks. The AL1032, a 10-GE (Gigabit Ethernet) switching processor from Allayer Communications, integrates one 10-GE port with 12 1-GE ports operating at full-duplex wire speed for an aggregate throughput of 44 Gbps. Flow-control circuitry increases back pressure in the event that all 12 1-GE ports simultaneously access the 10-GE port to maintain a steady 10-GE output. The 10-GE port enables LANs to connect directly into the Internet via OC-192 optical links. Other applications include terabit and multigigabit routers, high-port-density gigabit switches, and Ethernet/Packet over SONET. The device achieves wire speed on all ports at frames as long as 9 kbytes and integrates memory elements, such as the MAC (media-access-controller)-address table, VLAN (virtual-LAN) database, and frame buffers in an on-chip, 1-Mbyte SRAM. A Layer 2 to Layer 7 policy and quality-of-service engine provides higher layer switching functions without reducing switch performance. The 10-GE port also has a dual mode to support either a 10-GE LAN physical layer or an OC-192 wide-area-network physical layer. The AL1032 comes in a 785-bump TGBA and costs $250 (10,000). Get CMOS 802.11a for the price of 802.11b. Radiata based the R-M11a baseband modem and R-RF5 5-GHz radio transceiver on the IEEE 802.11a standard. The chip set targets wireless engines for homes and enterprises and supports data rates as high as 54 Mbps. The 64-tone R-M11a COFDM (coded-OFDM) PHY (physical-layer processor) has independent receiving and transmitting paths that support full-duplex operation. Modulation options include BPSK, QPSK, 16-QAM (16 quadrature-amplitude modulation), and 64-QAM. The device has dual receiving ADCs and transmitting DACs, as well as separate 8-bit receiving and transmitting data ports. Radiata manufactures the device in a 0.25-µm process. The R-RF5, with a seamless interface to the R-M11a, is a half-duplex transceiver for use in the 5-GHz unlicensed-national-information-infrastructure bands. Image-rejection mixers and on-chip filters, including a 20-MHz integrated-IF-channel filter, reduce external-filter requirements, as well as total system cost and size. The company manufactures the R-RF5 in a 0.18-µm process. Volume production is slated for January 2001. Price is $35 (100,000). A PCMCIA reference design is available. Enhanced FEC provides 3-dB headroom. Advanced Hardware Architectures can help expand your design options with its Astro OC-3 FEC (forward-error-correction) IC, which it based on enhanced (Turbo Product Code) technology. The approach provides as much as 3 dB more coding than Reed-Solomon or Viterbi coding. The encoder/decoder provides 155-Mbps data rates, and coded-channel rates exceed 200 Mbps. The device can operate in full-duplex mode with block as large as 16 kbits. A soft-input, soft-output decoder is responsible for the enhanced FEC by making intelligent corrections based on retained confidence information and iteratively correcting errors until it converges on a best result. Price is $100 (1000). USB 2.0 goes silicon. NetChip Technology's NET2290 USB 2.0 general-purpose device controller targets CPU-based peripherals. The NET2290 integrates an analog transceiver and includes a direct interface to many 16/32-bit CPUs, seven endpoints, 8 kbytes of FIFO memory, a high-performance serial-interface engine, and integrated configuration logic. The read/write cycle of the NET2290 is less than 15 nsec, enabling greater-than-1-Gbps burst data rates. The device also reduces the processing load on the peripheral CPU through built-in dual-channel DMA and multiple-buffered FIFO buffers. For example, a 4-kbyte FIFO memory can buffer as many as eight 512-byte USB 2.0 packets. (USB 1.1 uses 64-byte packets.) Double-buffering the FIFO memory means that you need not wait until the buffer is empty to preload packets, thus reducing the number of interrupts required to manage the buffers and maintain maximum throughput efficiency. The NET2290 in 128-pin TQFPs starts at $15 in volume quantities. Ternary CAM supports OC-768 speeds. SiberCore's SiberCAM Ultra-2M is a 2-Mbit, 100-MHz, ternary CAM (content-addressable-memory)-based packet-forwarding engine (Picture). The company guarantees that the device will perform one search result per clock cycle. Assuming one look-up per packet, the Ultra-2M can forward as many as 100 million packets/sec, supporting speeds as high as OC-768. A programmable compare-and-search word allows for support of narrow Internet Protocol Version 4 (IPv4) through wider Version 6 (IPv6) words and handles other Layer 2 through 7 protocols to support class of service, quality of service, packet classification, and virtual private networking. You can dynamically configure entries to support 36-, 72-, 144-, and 288-bit-wide comparand words, avoiding the loss of full usage of memory that traditionally occurs when the size of all entries must be fixed or the size of the longest entry in the table. The one, zero, and don't-care ternary states enable the device to meet classless-interdomain-routing and longest-prefix-match requirements. The Ultra-2M is available for $70 in volume. ADSL goes octal. Centillium's octal-port CopperFlite multimode ADSL (asymmetric-digital-subscriber-line) transceiver chip set includes the CT-L53AV08 analog front end and CT-L53CD08 DSP. They support as many as eight ports of full-rate Turbo G.lite or G.lite ADSL, including ITU G.992.1 (Annex A, B, C, and H), ITU G.992.2 (Annex A and C), and ANSI T1.413 Issue 2. It also supports multiple PVCs (permanent virtual circuits) for VoDSL (voice-over-DSL) applications with quality-of-service support and VoPCM (voice over PCM). The chip set requires no external memory, VCXOs, or glue logic and consumes less than 0.5W per port for a total consumption of 4W. You perform upgrades in software based on the programmable DSP. Other features include Utopia Level-2, bit-synchronous, and PCM interfaces for DSLAM (DSL-access-multiplexer), digital-loop-carrier, message-display-unit, and optical-network-unit applications. The chip set costs $200 in volume. Encryption algorithm makes systems harder to crack. The Tumbler software-tool kit from NTRU Cryptosystems implements NTRU, a public-key-cryptography system that the company claims delivers encryption, decryption, authentication, and digital-signature features more than 100 times faster than alternative systems. This generation of independent keys—those not based on keys used in a previous transaction—allows you to encrypt larger content, such as music and video data, with different keys, thus increasing the cost and difficulty of breaking into the content. The Tumbler tool kit costs $5000. The algorithm is also available for wireless systems through F@stWTLS, an implementation of the Wireless Transport Layer Security Protocol. |
Programmable-logic gate counts move up. Xilinx built its 1.5V Virtex-II FPGAs on a 0.12-µm effective-channel-length process with eight layers of copper-enhanced interconnect. Xilinx plans to begin shipping samples of the first Virtex-II parts by the end of this year. By midyear 2001, Xilinx claims, the Virtex-II family will span a range of 50,000 to 10 million system gates. Each Virtex-II Block RAM is 4.5 times larger than its previous-generation Virtex counterpart, including optional parity. In addition to further increasing the ratio of block-RAM bits to logic gates over previous-generation FPGAs, Xilinx supports two additional block-RAM operating modes. The first, read-before-write, finds use in single-clock-cycle-read-modify-write and similar applications. The other, no-output-change-write, is a fancy way of saying that Xilinx has added a latch to prevent read outputs from switching during write operations. With Virtex-II, Xilinx modifies the Virtex logic structure. Each Virtex-II configurable logic block now contains eight four-input look-up tables and eight flip-flop registers, twice as many as in Virtex. Look-up-table-to-look-up-table cascading and configuration-logic-block-to-configuration-logic-block interconnect enables the blocks to implement fast and wide multiplexers, long shift registers, and 128-bit distributed SelectRAM blocks in addition to traditional logic functions. FPGA family takes integration "serialously." QuickLogic's QuickSD devices are programmable-logic ASIC/FPGA hybrids, which the company calls Embedded Standard Products. The devices have as many as eight SERDES (serializer/deserializer, along with multiplexer/demultiplexer) data channels and two clock channels, all bus-LVDS for high-current and long-signal-drive capability (Picture). QuickLogic's approach puts the SONET logic in slower, more expensive antifuse FPGA gates, but, as a result, the parts are also more flexible, supporting other soft-core-based networking interfaces. Individual channel-timing control includes dedicated PLLs, optional CDR usage, pre-emphasis and equalization for long lines, and dc balancing for separate clock configurations. Data parallel bus-width options range from 1-to-1 to 20-to-1, and an external parallel clock can drive modes as high as 8-to-1. The three planned QuickSD family members have a core operating voltage of 2.5V, and I/O buffers run at 2.5 or 3.3V. The $48 (10,000) QL82SD and corresponding beta back-end design tool set are available. QuickLogic schedules the $25 (10,000) QL81SD and QL84SD to follow in the first quarter of 2001. Prices in all cases are for the cheapest commercial-temperature package option and lowest speed; the company plans to offer each device in three speeds. A flash in DRAM's clothing. Micron Technology puts an interesting twist on the DRAM interface with its first SyncFlash memory, the 3.3V, 64-Mbit MT28F4M16S2TG. Micron began with a DRAMlike internal architecture, package, pinout, and pricing structure. The company's approach puts the flash memory on a low-pin-count, guaranteed-cached system bus, which, in some cases, eliminates your need for other ASIC- or CPU-based memory interfaces. SyncFlash's 16-bit data bus supports burst read operations at speeds as high as 100 MHz (with three-clock column-address-strobe latency), and optional fine-pitch BGA packaging handles extended temperature requirements. You can test-drive the MT28F4M16S2TG now via a Denali Software (www.denali.com) provided model. Multilevel signaling technology boosts peak transfer bandwidth. The QRSL(Quad Rambus Signaling Level) signaling technology from Rambus gray-codes the data-bit combinations, both for improving noise immunity and for enabling the same chip to support both multilevel and conventional signaling. Instead of simply sampling the current on input pins at a clock edge, QRSL receivers integrate the values around the clock transition for improved transient rejection. Corresponding improvements in transmitter design enhance dynamic calibration and voltage resolution. Full-speed scope plots allude to the technique's validity, but the transition of low-volume laboratory experiments to high-volume system manufacturing is often more difficult than companies anticipate. Rambus is careful, therefore, to position QRSL as appearing first in short-channel configurations, such as the Nintendo 64 and Sony Playstation 2 game consoles, with a few components soldered directly onto the system board. Nintendo 64 a few years ago was RDRAM's first high-volume success story. QRSL won't even necessarily appear first in memory-interconnection applications, according to the company. Mushrooming multimedia data demands more memory. Digital-still-camera resolutions continue to rapidly climb upward. Consumers want to store more digital-audio files on their MP3 players. Digital videocameras with solid-state storage have even debuted. These and other multimedia applications put increasingly intense pressure on flash-memory manufacturers to cost-effectively increase the amount of data that can squeeze onto each chip. Toshiba with its single-die, 512-Mbit TC58512FT NAND memory becomes the latest vendor to respond to this trend. The 0.16-µm device is also available in a dual-die, 1-Gbit option, the TH58100FT, which allows you to create, for example, a 128-Mbyte SmartMedia card. Each die now contains four programming page buffers, versus the previous two. The TSOP-packaged, $140 TH58512FT and $280 TH58100FT were both scheduled to enter volume production during this quarter. DRAMs: bigger, faster, and wider. The trend toward DRAMs tailored for applications other than PC main memory continues with Samsung's latest 64-Mbit SDRAMs. The memories' 32-bit data buses decrease the required system-memory granularity for graphics frame buffers and other embedded applications. Double-data-rate interfaces running at 133 MHz transfer data on both clock edges, translating to 8.5 to 11.6 Gbps of peak throughput. FPGA heavyweight gets serious about hybrids. Altera this summer announced its Excalibur program, initially targeting the Apex 20K programmable-logic family and consisting of the Nios processor soft core and both ARM (www.arm.com) and MIPS (www.mips.com) hard cores. Altera's XA10 integrates a 200-MHz ARM922 core, including 8 kbytes each of instruction and data cache; 256 kbytes of dual-port SRAM; and 128 kbytes of single-port SRAM. The device will be available for sampling by year-end and will enter volume production in the first quarter of 2001. Altera plans to also embed the UART, interrupt controller, SDRAM controller, and timer/counter functions in an on-chip ASIC. The company will offer additional peripherals as soft cores housed in programmable logic, all interconnected via multiple AMBA (ARM's Advanced Microcontroller Bus Architecture) buses, the same interconnection scheme that Lucent plans to use with its hybrids. Close behind the XA10 will be the XM10, Altera's first MIPS-based hybrid chip. Specifically, Altera chose the 200-MHz MIPS32 4Kc core with 16 kbytes of instruction cache and 16 kbytes of data cache; single- and dual-port SRAM; and a single-cycle, 32´16-bit multiply-accumulator. Both ARM- and MIPS-based architectures will also come in smaller variants with less single- and dual-port RAM and programmable logic by midyear 2001, according to the company. And Altera has resurrected its MPLD (mask-programmable logic-device) program to provide lower cost, high-volume production variants of most of the devices. Prices start at $35 (10,000) for the XA1 and XM1 devices, $175 for the XA4 and XM4 devices, and $700 for the XA10 and XM10 devices. FPGAs up design flexibility. Based on Altera Flex 10KA FPGAs, the CL10KA family of ASICs shortens design cycles and increases design flexibility for cost-sensitive applications. The programmable Flex devices are used to prototype and debug CL10KA ASIC designs, offering an FPGA-based design flow that you can immediately and directly implement in a CL10KA ASIC. Vertical link-configured ASICs have a small die size and maintain full architectural compatibility with Altera FPGAs. All IP cores that have been optimized for the Flex 10KA function identically in the CL10KA. Clear Logic delivers ASIC samples within two weeks with no NRE or other engineering charges. Programmable SOCs provide slick designs. Atmel's FPSLIC (field-programmable system-level-IC) devices combine FPGAs having as many as 40,000 gates with SRAMs, a RISC µC, and other control and timing blocks. The combination, which the company touts as the first programmable SOC (system-on-chip) design, lets you correct or change design details on the fly. FPSLIC chips also provide in-system-programmable (ISP) capability, letting you dynamically change device functions during operation to account for changing system requirements. Each member of the AT94K FPSLIC family includes an FPGA block with 10,000 to 40,000 gates of logic and 4.6 to 18.4 kbits of distributed single- or dual-port SRAM in 32´4-bit blocks. Along with the FPGA is the AVR 8-bit RISC processor, offering greater-than-30-MIPS performance, more than 120 instructions, and low power dissipation. The device also has an on-chip hardware multiplier for complex DSP functions. Power dissipation for a full FPSLIC chip is 5 mA/MHz during operation and less than 1 mA in power-down standby mode. The System Designer EDA tool suite includes tools for design entry, project management, and hardware/software co-verification along with software for AVR µC and FPGA design and development. The suite operates under Windows and costs $495/year. Samples of AT94K FPSLIC devices will be available in December for $19.90 (20,000) for the member with 10,000 FPGA gates. Development kit targets Linux. The Embedix software-development Kit from Lineo Inc provides software tools for deploying Linux across a full range of embedded devices and systems. The kit leverages the CodeWarrior IDE from Metrowerks and includes a graphical-configuration tool and a complete version of a Linux-development host operating system. Embedix SDK for X86 costs $4995. Windows CE development kit generates XML components. The XML-based CE Transaction Builder development kit from Bsquare enables simple development of applications for Microsoft's BizTalk framework. The kit allows you to port legacy applications to BizTalk running on Windows CE-based devices and automatically generates XML schema-specific components for faster application development. The CE Transaction Builder costs $15,000 for an unlimited-use development license. Driver-development tool kit is Windows plug-and-play-compatible. Version 2.7 of BlueWater Systems' WinDK tool kit provides Windows 2000 plug-and-play and power-management support. It includes USB and IEEE-1394 features and lets you develop driver kernels in C and C++. Version 2.7 starts at $995. Real-time embedded-development tools run under Windows NT. The Rational Suite Development Studio RealTime Edition software suite integrates the Rational Rose RealTime 6.1 unified-modeling-language-based modeling environment. It performs automated runtime error and memory-leak detection, performance profiling, and code-coverage analysis. Runs under Windows NT. The tool costs $7250 for a node-locked license and $14,500 for a floating license. Tool improves Java applications. The Optimizeit 3.1 Professional Java-profiling tool from Intuitive Systems is available for both Windows and Solaris OSs. It lets you test and improve the performance of Java applications, applets, servlets, and JavaBeans and performs CPU profiling, performance tuning, memory-leak debugging, and real-time monitoring. The tool costs $449. Kernel-aware tool allows live-RTOS profiling. The Nucleus Plus Proview RTOS kernel from Accelerated Technology teams with Rtview's SurroundView application-monitoring tool. It allows live profiling of the RTOS and helps you understand the dynamic interactions between system objects. Nucleus ProView costs $2995/seat; bundled with SurroundView, it costs $4995/seat. Networked tools simplify software development. Software-development tools from IBM enable businesses to build applications that connect embedded devices to enterprise back-end systems over the Internet. Applications include vehicle communications systems, personal digital assistants, mobile phones, and home networks. IBM's VisualAge Micro Edition includes a team-oriented IDE for embedded-Java applications. Team development allows designers at remote locations worldwide to share code via a wide-area-network. Additional host-development tools include the remote debugger, Java compiler, profiler, editor, and smart linker. The embedded-processor runtime support includes the Java virtual machine, target optimized class libraries, user-interface routines and TCP/IC connectivity. The VisualAge Micro Edition supports PowerPC, x86, MIPS, and SH4 processors. Prices for IBM business partners start at $1000 (OEM). A free evaluation copy of the software is available for downloading at www.ibm.com/software/ad/embedded. RTOS-simulation environment works on target, host. The OSE RTOS (real-time operating system) from Enea OSE Systems targets the simulation and operation of the OSE RTOS. It operates on a target, as well as on the host in a running application. Prices start at $3000.
