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FROM EDN EUROPE: Autogenerate low-level code for SOC designs
By Graham Prophet -- EDN, 9/1/2000
Easi-Gen is a software tool that automates the development of the layer of software that interfaces hardware blocks—especially peripheral functions—within a complex embedded design. Its developers at Beach Solutions identify this task as one of the key activities—within the hardware/software integration and debugging phase of a system-on-chip design—that is both time-consuming and error-prone. The process captures detailed information about the hardware of your design and automatically generates access functions and macros. You use Easi-Gen by describing, via graphical interface, your system in terms of system-address map, peripheral cells, registers, bits, groups of bits, their polarities, and required programming sequences. The tool checks the input for duplications, address conflicts, and correct bus-width messages; it builds a database of information about the design, and its output is a set of automatically generated C functions comprising program code to correctly address the peripherals within the system. You can then access the functions by name, concealing all of the detail and imposing a consistent programming style. Output includes documentation in HTML format or RTF, a detailed reference manual, and a programmers quick-reference guide. Other parts of the system include a librarian tool to give an overview of a generated library and a peripheral configuration tool that aims to give rapid configuration of all the peripherals in a system, avoiding errors and producing optimised code. The tool set explores all of the available and legal options for programming the peripherals and presents these options to the programmer in menu form. Terry McCloskey, Beach Solutions vice president of sales and marketing, says that the tool automates, in a formalised and maintainable manner, information that all projects must generate; the company is working on generating the same data from a higher level description of the hardware system, such as VHDL or Verilog. Many bugs, McCloskey asserts, originate at this software/hardware interface level and manifest themselves only when code first runs. Formalised generation of this firmware layer can greatly reduce that bug count.
