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FROM EDN EUROPE: Connect short-range serial data streams with a link.
By Graham Prophet -- EDN, 9/1/2000
If you need to implement fast serial packet communications between two chips that can be on the same board or on boards separated by as much as 100m, a Link might be the way to go. Links—from UK-based company 4Links—are self-contained physical-layer-interface chips that implement a serial connection, handling all of the communications overhead and leaving the host system free to carry out its own task. You therefore need two Link chips (or IP blocks) to build a connection; 4Links offers products at the board, chip, and IP level.
4Links originally created the underlying technology behind the Link for the peer-to-peer links that connected the Inmos Transputer. The company subsequently developed the technology to become IEEE 1355; a version called SpaceWire is being developed jointly with the European Space Agency (ESA) and is in widespread use in satellite systems. 4Links' founder Dr Paul Walker says that Links combine the advantages of low cost, high performance, and fault tolerance. Links run at 100 Mbaud and higher, and you can achieve distances as far as 30m at 100 Mbaud using standard shielded-twisted-pair cabling. The architecture is similar to a distributed FIFO, transparently handling all flow control. The packet format is flexible; with header and payload are of arbitrary length. You can implement circuit-switched applications by following a header with an indefinitely long payload.
You can implement Links in less than 600 gates, and you can use them in place of a UART. In high volume, an integrated Link can cost less than 2 cents. You can use more than one on a single chip for greater bandwidth, and in the IEEE 1355 implementation, Links can reach gigabit-per-second speeds. The boards are available in PCI and CompactPCI formats; chips include a simple demonstration version of the 1355 link in a 44-pin, 64-macrocell PLD that runs at 50 Mbaud using external FIFOs and a 16-way packet-routing switch for the original 20-Mbaud standard. IP includes the C113, a licence for the third generation of Links running at 100 Mbaud. The licence includes three Links each with 18-bit-wide FIFOs. C112 is a licence for a 100-Mbaud Link that fits in the slowest version of the smallest Xilinx FPGA. IP for routing switches is also available, as is consultancy for custom designs.
You can find out more about IEEE 1355 at www.1355.org.
