Profile

• About Me

Recent Posts

• DesignCon 2008: One step forward, two steps….
• EDAC CEO Forecast: 2% growth for EDA revenue in 2008? EDA blues or blue skies ahead?
• My IC reliability cover story and my upcoming DesignCon DFM panel
• Brave, Brave, Brave Sir Robin…Saxby
• Calypto RTL to ESL equivalence checker gets vote of confidence
• "Let the mayhem begin!": Open Verification Methodology available for free download
• Congratulations on the Xilinx CEO gig, Moshe!
• 2007: the year of EDA isolationism
• EyeClops and IlluStory: more educational Holiday gifts for kids
• Living dangerously in EDA: microphone, you, Davidmann

Recent Comments

• The Real Deal on Cadence/EDA vet Eric Filseth takes over Ciranova: idealistic or insane (or both)?
• CitoupCithelp on Another Grim Day for EDA: Richard Goering laid off from EE Times--CMP layoffs
• CitoupCithelp on Another Grim Day for EDA: Richard Goering laid off from EE Times--CMP layoffs
• Steave on I’m no one trick pony!
• PhillDoc on Even EDA ex-Avanti CEO Gerald Hsu has a blog

Most Commented On

• How long should a TV last? (50)
• "How long should a TV last" and my new “Electronics Products Obituary” (26)
• EDA’s ESL vendors--Unite and take over!...or at least get organized (18)
• Grim day for EDA—Gartner closes down EDA analysts group (16)
• Another Grim Day for EDA: Richard Goering laid off from EE Times--CMP layoffs (12)

Archives

• February 2008
• January 2008
• December 2007
• November 2007
• October 2007
• September 2007
• August 2007
• July 2007
• June 2007
• May 2007
• April 2007
• March 2007
• February 2007
• January 2007
• December 2006
• November 2006
• October 2006
• September 2006
• August 2006
• July 2006
• June 2006

By Category

• Analog (12)
• ASICs (49)
• ASICs (23)
• Automotive (1)
• Business and Marketing (9)
• C++ (1)
• Co-verification (1)
• Communities (21)
• Compiler (1)
• Components, Hardware, Interconnect (2)
• Compression Algorithms (1)
• Configurable Processor (1)
• Configurable Processor (5)
• Connectors and cables (1)
• Consumer Electronics (1)
• DAC (3)
• Defense (1)
• Design and Technology (4)
• Design for Reuse (3)
• Design Ideas (1)
• Design Strategies (3)
• Digital ICs (28)
• Displays and indicators (1)
• DSP (3)
• Economics (1)
• EDA (116)
• Embedded Systems (2)
• Executive Changes (2)
• Finance (3)
• HDL (7)
• HDL (7)
• Interconnection (1)
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• Languages (6)
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• Management (5)
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• More News (1)
• Opinion/Analysis (2)
• Packaging (1)
• Passive components (1)
• Processors (10)
• Processors & Tools (1)
• Programmable Logic (19)
• Reconfigurable and reuse (6)
• Relays and switches (1)
• Research (1)
• RTOS (1)
• Schematic Capture (5)
• Semiconductors (17)
• Show Daily Report (3)
• Signal Integrity (1)
• Simulation (10)
• SOC (8)
• SOC (1)
• SOC (4)
• SOC (System on a chip) (23)
• Software (1)
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• Software Development Tools (4)
• Spice (4)
• Standards (1)
• Structured ASICs (1)
• Supply Chain (1)
• Synthesis (5)
• Synthesis (4)
• System-level Design Language (6)
• Test and Measurement (1)
• Test Bench (6)
• Venture Capital & IPOs (4)
• Verification (9)
• Verification (3)
• Vertical Markets (1)

IC Design Articles

• Mentor assembles a test-yield fusion platform
• EDN on IC Design: Debugging FPGA designs may be harder than you expect
• Intel, Numonyx to describe stackable phase-change memory array
• ARM IP group wrestles complexity of 32-nm physical design
• Debugging FPGA designs may be harder than you expect
• More...