Between The Lines

I attended DesignCon last week and covered two events: “Where’s the ROI on DFM?”, which was a lively business panel, and a panel moderated by EDA industry analyst Gary Smith on functional verification.

I actually planned to write-up a few more events but was sad to find that the others I attended lacked substance and were largely product and/or marketing pitches. I’ve been attending DesignCon my whole career from the days when it was called Design SuperCon and was run by HP. I’ve moderated several panels over the years and even hosted technical tracks. A few years ago, the IEC took over the conference and actually improved it. I think the shows back in 2006 and 2007 were both great with some strong keynotes and panels as well as t...Read More

Just got back from the EDA Consortium’s annual EDA CEO Forecast and for the most part the CEOs seemed particularly gloomy when it came to revenue forecasts for the year. In brief, the CEO’s didn’t offer any forecasts but Mentor CEO Wally Rhines, whose company is in a quiet period and thus could not give a prediction for EDA industry growth in 2008, pointed to a report from one of the financial firms that showed a historic correlation between semiconductor R&D expenditures and EDA revenue for the last several years. If the correlation holds true to form, the analyst report extrapolates that the EDA industry will only grow 2% in 2008. None of the CEOs on the panel disputed that number.

It is worth noting that Synopsys’ CEO Aart de Geus could not offer a prediction because like Rhines his company is in a quiet period and has yet to report its qu...Read More

Hi folk, I’ve been in hunkered down mode for the last few weeks researching and writing my next cover story. This one’s on IC reliability. It’s a subject I haven’t tackled before and quite frankly is a subject I haven’t seen too much coverage about, even the EE trade books.

I actually learned a quite a bit of information about how design groups and more so semiconductor companies and IC manufactures look at reliability throughout product development. It’s actually a story that could have been a small novella. In print, space is always a bit limited so the print version of the story will cover the more traditional failure mechanisms designers and manufacturers need to watch out for. Some of those failure mechanisms pop up one process generation then are handled quickly by the semi guys. Some failure mechanisms are starting to rear their...Read More

EDN’s sister publication Electronics Weekly has a video clip of ARM’s Sir Robin Saxby receiving the Elektra Lifetime Achievement award…way to go Sir Robin!

A few years ago when EDA startup Calypto introduced its SLEC (sequential logic equivalence checker) tool, I thought it was a very promising technology. One of the biggest issues in ESL modeling is ensuring that the block or design you are modeling at an ES level (in C++, SystemC or ANSI C, etc.) is functionally the same as the RT level implementations. Not having a way to tell if they are the same is a bit of a roadblock. Also, for ESL synthesis to reach its full potential, designers would need a way to ensure the ESL output of a given synthesis tool was functionally the same as the RTL version and vice versa.

When Calypto introduced SLEC a few years ago, it showed great promise in solving those problems. The tool claimed to check that models and synthesis output at different levels were essentially the same. The to...Read More

Hi folks, the contentious SystemVerilog tool interoperability standard the OVM (Open Verification Methodology) co-developed by Cadence and Mentor Graphics is now available for download.

Mentor and Cadence are distributing the OVM under an Apache 2.0 license. It includes the OVM source code, documentation and use examples. You can access the license and download at www.ovmworld.org.

If you want more background on the OVM check out my write up from last year, “Cadence and Mentor create free, open-source SystemVerilog methodology.” After writing the announcement up, I heard from both Mentor Graphics and Synopsys and learned very quickly it’s a touchy subject among verification tool vendors (see Between the Lines bl...Read More

Hi folks, while I was away on vacation, Xilinx prebriefed the press corps about news that EDA veteran Moshe Gavrielov has been appointed the new CEO at Xilinx. Ann Mutschler covered it for us and Ron Wilson blogged on it. First off I’d like to say Congratulations Moshe and Congratulations Xilinx!

It will be interesting to see how Gavrielov transitions from the EDA to the FPGA world and how he tackles heading up a company that is larger than the biggest EDA company. I’m sure a lot of folks are asking why is a guy who has never headed up a semiconductor company and was the CEO of a relatively small, publicly held EDA company being appointed the CEO of the programmable logic industry’s biggest company? I personally think it’s a...Read More

I saw somewhere that the word of the year--that is, the word of 2007--was “subprime.” In the EDA industry, I think many EDA watchers would say the word of 2007 was “consolidation.” I personally think the word that best describes EDA in 2007 is “isolationism.”

2007 turned out to be a pretty good year for EDA revenues. There was a decent amount of M&A and I don’t remember a single lawsuit being filed. I count it a pretty good year in EDA when I don't have to spend time interviewing lawyers regarding claims and counterclaims.

I think it’s pretty much been the case for many years that the big 4 in EDA have owned more than the lion’s share of overall EDA revenue. But in 2007, it seemed to me, and maybe it’s just me, that the top executives at the big 4 really started to flaunt it.

But it isn&rsqu...Read More

A couple of my colleagues here at EDN have been busy posting Holiday Gift Guides for Engineers. Check out Brian Dipert’s post Brian's Brain's Holiday Gift Guide for Engineers and Margery Connor’s post PowerSource's Holiday Gift Guide for Engineers for some really cool gift ideas for the engineer in your life.

Last year, I posted my own gift guide but this one was for the kids in our lives. That post is called “Xbox, Zombies, Lego, PC Boards and better mouse traps: educational high tech toys for Christmas.”

All the gifts mentioned in my previous post are still in great...Read More

Last week I interviewed Simon Davidmann about his not so new startup Imperas. You can read my interview by clicking on the story “EDA ESL startup Imperas close to launch.”

I’ve known Simon for many years and I think he’s certainly one of the big characters in EDA. Back in the days when the industry was debating over which language, Superlog (later known as SystemVerilog) or SystemC, should be THE next design and verification language (the next step up in abstraction layer beyond Verilog or VHDL), Davidmann was a relentless advocate/marketer of his company’s language, Superlog. To augment a phrase from my former colleague Brian Fuller, one of the most dangerous places to be is between Simon and an open microphone.” If the subject was ESL, Simon was there--I remember Davidmann takin...Read More

We've just posted our HOT 100 products for 2007. This year the EDA industry produced quite a few interesting tools spanning several different design disciplines.

In 2005 and 2006, a vast majority of the EDA startups and new tools seemed to be in the DFM space. I think 2007 will likely be remembered as the year in which the big EDA vendors consolidated the DFM tool space and integrated many of these DFM tools into their RTL-to-GDSII tool flows.

But it will also be remembered as a year where there was a decent batch of EDA offerings. And the tools in the Hot 100 covered the gambit: from functional verification, to emulation, to timing analysis, place and route to IC and package co-design.

I’m pretty happy because 11 EDA products made it onto the final Hot 100 list and there are a total of 12 cate...Read More

It’s been quite a while since a product release has caused such a big reaction in the EDA industry. I’m sure all the big EDA players offering tools in the place and route world have busy on their phones today speaking with financial analysts, whom are wondering what EDA place and route startup’s ATopTech’s announcement means?

Early this morning ATopTech announced a triple whammy: they officially announced their company, their floorplanning to GDSII tool suite, and to top it off that they won a contract at big customer Broadcom.

This story started to get legs a few months ago, when John Cooley interviewed then Cadence executive Eric Filseth. The interview essentially claimed that there were some shenanigans going on...Read More

Hi folks, there’s interesting video interview on the street.com, in which Cadence CEO Mike Fister is being interviewed about the state of the semiconductor business. Big cheers to Cadence’s PR for setting up the spot. But the interview somewhat illustrates a sad truth: EDA still tends to be a bit too esoteric for the general business press.

You’ll note that in this interview, no one really defines EDA or what it is—the broadcaster refers to Cadence as a semiconductor supplier??? What does that mean? If you are semiconductor-tech savvy and especially if you are EDA savvy, you probably can follow what’s going on in the interview (though a times it seems somewhat a conversation in the boiler room...Read More

A few weeks ago I attended a keynote at ICCAD in which, Jeff Welser, director of the SRC Nanoelectronics Research Initiative (NRI), outlined industry efforts to find a replacement for CMOS. Our coverage of that keynote is “CMOS running out of gas, new effort looks for scalable replacement, ICCAD keynoter says.”

In his presentation, Welser whipped through a plethora of fascinating, eye catching foils describing the innevidable fate of CMOS and the need for scalabe predecessor. But one of the foils that really caught my eye was a foil discussing the long practice of “chip binning” and how it is in jeopardy mainly because of transistor leakage issues.

Chip binning has always been fascinating to me on many levels. What is it? It’s essentially a practice in which chip manufacturers ...Read More

‘Tis the season for not only Eggnog, Santa Clause and Seasons greetings, here at EDN it’s time for nominations for our 2007 EDA Innovations of the year award, but the deadline is fast approaching.

A few years back when I joined EDN, I started work after the selections for the 2004 Innovation award had already been submitted and the finalists selected (I had no say in who made the finalists lists but did get to put my vote in for a winner). I have to say though the list was of finalists for the EDA category was pretty weak. One finalist was something like version 6.0 of a tool that had been out for a decade, the second was a two-year-old tool from a pretty interesting startup and the third was a part-procurement tool from a big chip vendor (in my book it wasn’t even an EDA tool—it was a chip sales tool for that vendor but with a hook that allowed ...Read More