Between The Lines

Sep 1 2007 8:00AM | Permalink | Email this | Comments (0) |
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(Continued from “Who is the EDA leader in SystemVerilog? Part 2”)

Cooley’s survey, which seemingly addresses SystemVerilog usage directly, indicates that 65.6% of respondents are using Synopsys VCS for SystemVerilog, while 27.3% are using Mentor Questa or ModelSim, and 24.7% are using Cadence NC-Sim. If you add up Mentor and Cadence SystemVerilog usage that makes 52% (many users use a mix of or own more than one simulator), so OVM certainly has some market pull but is still seemingly smaller than Synopsys’. (Of course, vendors that don’t get favorable responses inevidably claim that Cooley’s surveys are unscientific or point out that Cooley actually tells vendors to get their customers to respond—essentially stuffing the ballot box, but Cooley’s survey’s in my opinion, while not 100% right, have proven to be very accurate—check out Cooley’s old place and route tapeout coverage).

All that aside, the OVM group believes that the openness of their effort will soon sway folks to OVM-based solutions, especially if Synopsys act proprietary with its own VMM. Indeed, the Mentor and Cadence folks I spoke with for my original VMM write up mentioned that they formed OVM out of necessity, in large part because Synopsys has made it next to impossible for competitors to adopt the VMM implementation into their tools. Wally shed a bit more light on this claim.

Wally says the VMM implementation licensing agreement competitors have to sign to join VMM is essentially worded to ensure that no competitor can participate. He read a couple of the more pointed clauses, summarized as follows:

VMM is only available for internal use (EDN translation: you can’t make a product out of it)

Synopsys has the right to terminate usage with 30 days notice for convenience (EDN translation: they can terminate the license for no reason at all).

I shared Wally’s claims with the folks at Synopsys and Yvette Huygen, Synopsys PR director, looked into it and responded:

“Wally must have seen some old version of the contract since neither of the clauses you present are in the current contract for the class libraries. The license agreement we offer to SystemVerilog/VMM Catalyst Program members enables them to redistribute a compiled version of the library, so anyone can implement the VMM in their product. In fact, we are aware of at least one non-Synopsys customer company that has an independent implementation of the spec. Furthermore, we give members very specific distribution rights for the VMM standard library at no charge.”

Yvette further noted: “As for Synopsys having leadership in SystemVerilog, I'd say Cooley's survey speaks for itself on this particular data point.”

So, indeed, while the OVM effort has its good side in proposing an industry standard SV methodology, it also has an ulterior motive. Still, it seems like a good deal and one of those things we wish all vendors would join.

It will be interesting to see who ultimately wins. For now questions like--Who has the best SystemVerilog simulator? Who is the SystemVerilog simulation marketshare leader?--are still not completely clear. Today it’s up in the air: a game of claims-- “he said, she said.” Perhaps next year we’ll get further datapoints and even maybe all the vendors will open their books so Gary or some other analyst group can truly identify the leader in SystemVerilog simulation. Of course, the analyst would have to create a “SystemVerilog usage” category, first.

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