Between The Lines

(Continued from “Who is the EDA leader in SystemVerilog simulation? Part 1”)

 Gary Smith has started his own research firm GarySmithEDA. Gary said he’ll soon release his marketshare numbers. But there’s a problem: Gary’s report currently covers SystemVerilog under “mixed language simulation” tools but it doesn’t cover SystemVerilog simulation usage of those tools (evidently there are no pure SystemVerilog simulators to report). Mentor Graphics has traditionally held the lead in mixed-language simulation because the claim to fame of Mentor’s ModelSim simulator (now Questa) is that it does Verilog and VHDL simulation from a single kernel. Shortly after Mentor released its mixed language simulator in the mid 90s, the other vendors followed suit. Traditionally, Synopsys and Cadence have had higher share than Mentor in pure Verilog simulation, while Mentor has enjoyed majority share in pure VHDL simulation [VHDL has always had its strongest following in Europe and there are a ton of FPGA designers who use VHDL still and undoubtedly many use Mentor for that purpose (but it remains to be seen if they using it for SystemVerilog and if they are using full versions (and full priced) of ModelSim/Questa?)]. That’s not to say users don’t find it a great pure Verilog simulator.

Gary was kind enough to give me a preview of the upcoming report and shared the numbers for the year 2006 and some historical data, as well.

In 2004, when Gary’s group was still at Gartner, they reported Mentor had 35% of the mixed-language simulation market, while Cadence had 34%, Synopsys had 31% and Aldec had the remaining 1%.

Gary’s group was laid off from Gartner before the group could issue its report for the year 2005. However, he shared those previously unreleased numbers: Mentor 36%, Synopsys 32%, Cadence 32%.

Gary says that his 2006 report will show that Mentor has 35%, Synopsys has 34%, Cadence 30%, and Aldec has 1% of the mixed language simulation market.

(As a side note I also asked Gary about his methodology. One of reasons his group was having trouble at Gartner was that some of the large EDA vendors would not open their books to Gary’s group (reportedly the main reason Gary’s group was let go was because they weren’t drawing enough revenue/selling enough reports). Gary noted that all the big vendors have refused to open their books at one time or another but for the 2005 report, Cadence and Synopsys both refused to open their books. He notes that this year, for the upcoming EDA report on the year 2006, Synopsys and Mentor have opened their books but Cadence has not. He said when that happens (when vendors don’t open their books and let Gary figure out share), the group employs a combination of several methods to derive marketshare numbers—the most effective of those is simply to call customers and ask them what they are using.)

Gary says that Synopsys had some internal problems in the 2002 and 2003 time frame but has since started to build momentum in the verification space. He attributes a small part of that gain to Synopsys releasing its VMM with ARM, before the competition.

And indeed Wally concedes that Synopsys VMM (and class libraries?) likely has a larger user base than either Cadence or Mentor’s individual SystemVerilog methodology manuals because Synopsys and ARM released VMM months before either Mentor or Cadence released their own, and years before Mentor and Cadence teamed up on OVM.

I then spoke with the folks over at Synopsys and they claim that not only do they have a big jump on the competition in SystemVerilog having released VMM months before Mentor, Synopsys also claims to have the lead in SystemVerilog simulation usage, noting that numbers from Cooley’s most recent verification,” survey seems to back up Synopsys’ claim….Continued at “Who is the EDA leader in SystemVerilog simulation? Part 3”