Between The Lines

A year or so ago, when Chartered, IBM and Samsung introduced their common process fab alliance, the CIS Alliance outlined what seemed like an overly ambitious, pie-in-the-sky plan in which the CIS Alliance would form a common DFM flow by picking best of class tools from disparate tool vendors.

At the CIS launch, I pointed out that EDA companies have had a terrible track record when it comes to tool interoperability and that fabs have been very reluctant to share sensitive process models with EDA vendors, fearing the models would fall in the wrong hands. So quite sarcastically I asked the CIS presenter if the CIS Alliance planned on having the flow together by 15nm node? Judging from the applause of users in the audience, others shared my skepticism. Wouldn't you know it, one year later, I'm eating a bit of crow, but I don't mind it—as the CIS Alliance has indeed put together a DFM flow composed of tools from a variety of vendors. And what's more encouraging, the CIS Alliance and other fabs like UMC and TSMC are all reportedly providing the models freely, at least for their biggest customers' 65nm designs.

Confirmation of this latter point came today from Qualcom's Matt Nowak at the Design Automation Conference panel "The Fabless Model: Is DFM Our Salvation or Demise?" "Last year the key question with regards to DFM simulators was will the foundries provide the models that are going to drive these simulators," said Nowak. "Now we've crossed that bridge, [the fabs] are fully engaged."

But Nowak said there is still work to be done: "Now we think the next question on the table is how do we standardize these models and make the tools interoperable? That in our minds is the next big step we need to take."

Nowak outlined how in the early years of SPICE simulation, there were several proprietary flavors of SPICE models and therefore several tools that didn't work together. "As time went on the models evolved from proprietary to standard and the simulators went from closed point tools to interoperable tools," he said. "And when that happened, it allowed the industry to go to higher levels of abstraction: first up to static timing analysis and now more recently to behavioral models. We believe in a similar fashion, DFM needs to evolve. And the first step needs to be to open up the standards.

Nowak said that initially, DFM was a set of rules and guidelines that the foundry provide. "Now we've moved to this simulation-based layout optimization, where we use simulators to identify hotspots in the design, then the designer goes and fixes those hot spots," said Nowak. "Where we need to go to next is 'cost-driven design.' We want to be able to do tradeoffs between yield, performance, signal integrity and power at the designer's desktop, and we want to be able to do it at a high enough level of abstraction so that we can incorporate these tools throughout the whole flow. For example we want to be able to tie the lithography and CMP simulation into extraction so we can take that throughout the flow. We think the next step after that is to push process awareness up to the architectural level using tools and methodologies so we can make architectural tradeoffs with process awareness and realize from that a true lifecycle cost optimization for every product."

In that presentation, Nowak succinctly outlined the promise and grand vision of DFM. I have to say I share it. And, while as an editor remain skeptical as to whether EDA, semiconductor and manufacturing equipment industries can work together efficiently to fulfill Nowak's vision before the 15nm node, I’m more than happy to eat another serving of crow.