Between The Lines

DAC is a place to absorb many things—new design trends, new companies, the health of the EDA and semiconductor industries. This year low power is by far the biggest theme of the conference and there's been a lot of knowledge to absorb on the topic here. I attended a couple panels on low power earlier this week and even moderated one here today with the authors of the newly released low power methodology manual, which discusses how Synopsys and ARM engineers applied several low power techniques to produce an ARM based SoC. I was very pleased to see that well over 240 folks attended the panel. One of the first things I always do when moderating panels is ask for a show of hands to see how many real chip designers are in the audience. And when I did it at this panel, around 220 of the attendees identified themselves as IC designers. I said to myself, “wow, that’s a great turn out” and jumped on the opportunity to ask the attendees a few more questions. When I asked the audience how many of them are designing their next projects at the 130nm node or lower, none, that’s NONE, said they were doing it. I then asked how many were at 90 nm? About 40% raised their hands. Then I asked how many were at 65nm. I was shocked to see that just about the remaining 60% raised their hand—there were just a few folks who raised their hand when I asked if they were targeting a process node of 45nm or lower.

Still, wow, that’s a whole lot of folks already at 65nm and a whole lot of folks who are interested in low power design techniques, which are certainly becoming mainstream.

Last night I also absorbed a healthy amount of libations at the Denali party and some other place…it’s a bit foggy but I remember one of my Brit friends/editors almost got trounced by a local. At any rate, a bit short on sleep, I was feeling a bit snappy at the end of the panel and aired my dislike of covering standards efforts (see sippy cups blog), so I conducted a similar poll regarding the battle between CPF and UPF. Not really surprisingly at a Synopsys event, zero raised their hand when asked if they want CPF to win. Only a few raised their hand when I asked if they want UPF to win (which I quickly realized was not a popular or desired response or desired question at a Synopsys organized event because Synopsys backs UPF). But everyone else raised their hand when I asked “How many of you just don’t care and want the vendors to finally pick one standard and go with it.”

It’s always been my hunch that EDA users and thus my true target audience just don’t care about the daily back and forth whining and politics of EDA standards. They just want vendors to pick one standard quickly (one that works, of course) and everybody support it. I’ve heard repeatedly that CPF and UPF are 85% the same, so it isn’t even a huge ramp up to change what's already been done in tools to support one of them! I’ve also heard a rumor at DAC that Cadence is a secret member of UPF but requested its name be stricken from any documents that relate that nugget. I further believe that CPF and UPF are only a temporary fixes anyway and that a really comprehensive power standard would also require hooks for thermal analysis ((all this leakage power is eventually going to get worse by gradient temp and by in-situ ambient temp issues (probably requiring real system models--Alberto Sangiovanni Vincentelli-type system level models?). That means they better get this one done lickety-split so they can do the next more comprehensive one. But all in all—it seems users, at least at this panel, don’t care about the drama. People have been saying that EDA is becoming a mature industry. HA! You only have to look at this segment to see it’s still as Steve Schulz, years ago when he was at TI, once described it: an adolescent industry. Pick a standard and serve your customers!