EDN Senior Editor Mike Santarini covers digital design and the EDA, ASIC, and FPGA industries. [Editor's note: As of Feb. 2008, this blog is no longer active and is presented here for archival purposes.]
Dec 18 2007 12:30PM | Permalink | Email this | Comments (3) |
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Last week I interviewed Simon Davidmann about his not so new startup Imperas. You can read my interview by clicking on the story “EDA ESL startup Imperas close to launch.”
I’ve known Simon for many years and I think he’s certainly one of the big characters in EDA. Back in the days when the industry was debating over which language, Superlog (later known as SystemVerilog) or SystemC, should be THE next design and verification language (the next step up in abstraction layer beyond Verilog or VHDL), Davidmann was a relentless advocate/marketer of his company’s language, Superlog. To augment a phrase from my former colleague Brian Fuller, one of the most dangerous places to be is between Simon and an open microphone.” If the subject was ESL, Simon was there--I remember Davidmann taking over an ESL panel one year at the DATE conference and he wasn’t even on the panel--snatching up most of the notable quotes for our coverage of it. That was pretty typical of Simon in those days.
But all kidding aside, his perseverance paid off when he sold Co-Design to Synopsys for a pretty penny and at the same time helped provide the design community with a new language and helped shape a direction for design languages for years to come.
It has panned out that SystemVerilog has evolved into the next HDL, a superset of Verilog that can handle assertion based verification, while SystemC has settled into the role of being a pretty suitable ESL verification language and promises to become a suitable design language and possible successor to SystemVerilog as design methodologies evolve.
So now that Simon’s next company is about to launch, and he’s tackling yet another really hard problem—multi core modeling and programming--we can bet he’ll be at it again. Certainly there’s been quite a bit of hype about Imperas long before it even launches, but what’s encouraging is that Simon thus far has proven he can back up the marketing. It will be interesting to see if he can do it again. In the meantime, if you’re attending an ESL or multi-core SoC design panel, remember to look both ways before walking up to an open microphone. Simon is surely on his way….
Related entries in: Configurable Processor | EDA | HDL | Languages | Reconfigurable and reuse | Simulation | SOC | Software Development Tools | System-level Design Language | Test Bench | Verification |
