Between The Lines

Hey folks, the huge news I referred to in my post on Friday has finally been announced. The huge news is that Ciranova has figured out a way for third-party layout tools supporting Open Access to read Cadence PCells. This morning we posted an analysis piece on the release.

While the Ciranova announcement may not be as "sexy" as a new RTL-to-GDSII system or a completely new tool category, it certainly has the potential to have a massive impact on the full custom and analog tool spaces and may help make inroads to establishing an industry standard process data kit.

The tool basically opens up Cadence PCells to the rest of the industry. Cadence has been withholding its PCell description format, SKILL, from the rest of EDA industry for over a decade and it has given Cadence a huge competitive advantage and allows it to maintain overwhelming marketshare in full custom and analog layout. Barring access to it has raised the barrier of entry for tool competitors and designers wishing to try out new technologies, as foundries and IDMs have typically created PCells for Cadence Virtuoso long before they create versions for systems that compete with Virtuoso. For years, EDA vendors, fabs and IDMs and customers, and commentators, have been asking Cadence to open up SKILL.

Last week I discovered that Cadence was supposed to have released it long ago by FTC order:

Last week, I moderated a panel on the need for an industry standard process data kit (PDK) and in doing some research for that panel, I stumbled across something on the FTC site that seems to have great significance. It turns out that as a condition of approving Cadence's acquisition of Cooper and Chyan Technologies back in 1997, the FTC (if I'm reading this correctly) ordered Cadence to give competitors equal access to its proprietary PCell description language, SKILL. You can read about that in my blog post "Tick Tock—in May 2007 Cadence's Federal Trade Commission ordered "openness" goes off the clock; and A HUGE EDA release."

I've since heard from a couple of Cadence competitors saying they are now looking into it and that "some action" may come out of it.

I guess the big questions are: why didn't competitors look it up years ago and press for enforcement? Why hasn't the FTC been on top of it (because Cadence was suppose to file a progress report every year describing how it is complying with the order)? And if competitors are finally able to get the FTC's attention before the 10 year order is up in May, what if anything will take place? The FTC certainly hasn't been on top of things concerning this order, but for that matter, neither have Cadence's competitors in this space. The order has been in effect and available for public consumption for NINE years—that's nine years Cadence has been ducking the order, and nine years that competitors in EDA have been held back from offering tools fairly to designers, NINE years Fabs and IDMs have had to spend time creating different version of libraries. Custom and analog design has been stagnant for 15 years; it would be nice to see a level playing field so this area can see some healthy competition and hopefully more innovation. It certainly has potential for growth as processors, memory, analog and analog/mixed signal ICs becomes large and more complex. Maybe the EDA Industry will become larger too?