EDN Senior Editor Mike Santarini covers digital design and the EDA, ASIC, and FPGA industries. [Editor's note: As of Feb. 2008, this blog is no longer active and is presented here for archival purposes.]
Nov 26 2007 1:31PM | Permalink |Comments (0) |
A months ago, I ran into blogger and verification specialist JL Gray and he gave me a copy of his business partner’s new book “Aspect-oriented programming with the e verification language—A pragmatic guide for testbench developers.” The author of the book and JL both work at Austin, TX-based design services company Verilab and over the years both have become devout users of the e testbench generation language that runs the Specman Elite testbench generation tool that Cadence gained in its acquisition of Verisity a few years back.
The e language was one of the first testbench generation languages but over the years has come under great criticism for not being a 100% open language. Whether it is sufficiently open or not has been the subject of many articles over the years, but that uncertainty has been enough for competing companies to start backing OpenVera and more recently SystemVerilog as predecessors.
And indeed there are quite a few papers and seminars out there to help e users convert to SystemVerilog and vice versa.
But in his book “Aspect-oriented programming with the e verification language,” Robinson doesn’t spend too much time bashing alternatives but rather goes to great lengths to present a very pragmatic approach for using e for aspect-oriented programming.
In brief, the book instructs users on how to reuse testbench code [create eVCs (virtual components)] and cleanly add new features to existing code without having to too intrusively modify the code base.
So if you’re a verification engineer, it may be worth your time to give it a read. Incidentally, the book is published by Morgan Kaufmann, which is associated with EDN’s parent company Reed Elsevier.
Related entries in: Languages | Reconfigurable and reuse | Simulation | Test Bench | Verification |