Between The Lines

Hi folks, the contentious SystemVerilog tool interoperability standard the OVM (Open Verification Methodology) co-developed by Cadence and Mentor Graphics is now available for download.

Mentor and Cadence are distributing the OVM under an Apache 2.0 license. It includes the OVM source code, documentation and use examples. You can access the license and download at www.ovmworld.org.

If you want more background on the OVM check out my write up from last year, “Cadence and Mentor create free, open-source SystemVerilog methodology.” After writing the announcement up, I heard from both Mentor Graphics and Synopsys and learned very quickly it’s a touchy subject among verification tool vendors (see Between the Lines blog entries “Who is the EDA leader in SystemVerilog simulation? Part 1and “Part 2.””

The Mentor and Cadence OVM effort was largely created in response to Synopsys and ARM’s Verification Methodology Manual. Cadence and Mentor claim that while they are releasing OVM months behind Synopsys’ VMM, the big difference is that OVM is completely open. Meanwhile, Synopsys claims VMM is and always has been open and furthermore is already well established in the user community.

So with OVM now released, it will be interesting to see which format the user community will back. Will it be VMM, OVM or both? Will one become a de facto or perhaps even standard (maybe IEEE standard)? Feel free to use the comments section below to share your preference(s). I’m sure your fellow engineers will find it useful.

As a villain media mogul in one of the 007 movies once said, "Let the mayhem begin!" Wuahahaaaa!