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Mike SantariniEDN Senior Editor Mike Santarini covers digital design and the EDA, ASIC, and FPGA industries. [Editor's note: As of Feb. 2008, this blog is no longer active and is presented here for archival purposes.]



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Friday, July 14, 2006

Mentor Graphics: All your apples in one boat?

Jul 14 2006 3:58PM | Permalink |Comments (5) |


Now that Cadence has made its big pre-DAC announcements, Mentor recently took its turn unveiling its big announcements for DAC. Mentor had two primary announcements leading up to the show and both of them are quite frankly ho hum product upgrades rather than new technology announcements. The first one announced that Mentor made its ANSI-C synthesis tool capable of full-chip synthesis.

The second one, which a Mentor PR person called "Mentor's most significant product announcement of the year," turned out to be an upgrade of Mentor's flagship product Calibre. Mentor apparently wanted me to write a giant 600 word puff piece on it, like my competitors, but quite frankly it isn't worthy.

Here in a nutshell is what Mentor announced: the new Calibre nmDRC in a 40-CPU cluster now runs a full design in less than 2 hours and has higher capacity than the older version because all the good functions in Calibre have been moved onto a new hyperscaling architecture. The new version can also perform localized fixes so you don't have to do full DRC reruns, you can simply rerun the problem areas. Oh and the new tool now supports TVF as well as SVRF.

I'm sure it isn't an easy feat reworking a tool so that it runs faster and has a higher capacity, but essentially you hear that in any and all EDA upgrade releases. So you may be asking: What, no new cool tool from Mentor? Mentor does believe this is the big one. And to Mentor it is.

Certainly the meatier story is not the technology innovations added to Calibre, it is the business story here—the importance of Calibre to Mentor. You see Mentor's Calibre has downright owned the digital ASIC and SoC DRC/LVS tool market for about six years. And Calibre today represents the largest chunk of Mentor's revenue. I'm not sure how large a percentage of Mentor' yearly revenue it represents, but I bet it is huge. But over the last year, Calibre has gained renewed competition from Cadence and Magma. Both of those companies claim Calibre's Achilles heel has been its limited capacity and performance and thus both companies introduced DRC/LVS technologies claiming better run times. Mentor with nmDRC claims to have now at least matched the run time claims of both Magma and Cadence. So the message Mentor wants you to come away with here is that Calibre is still as accurate as always and is now as fast if not faster than competing tools, so don't buy another tool.

Certainly if Calibre falters, Mentor has to transfer its flag from the Calibre battleship to its next biggest boat in its fleet—at last call that's the ModelSim/Questa mixed language simulator. How big is the Questa boat? Even if you believe VHDL's going to reemerge as the design language of the future, I bet it's big enough to ski behind but not big enough to go to war with. Mentor's going to need a bigger boat and thus a real physical design suit sooner or later. Synopsys outbid Mentor for Avanti. Magma's legal situation is likely too messy. Keep an eye on Sierra Design…


Related entries in: Communities | EDA | SOC | Verification | 


Reader Comments



at 7/17/2006 10:33:54 PM, Developer said:
"I'm sure it isn't an easy feat reworking a tool so that it runs faster and has a higher capacity, but essentially you hear that in any and all EDA upgrade releases."

I think you are wrong in "essentially you hear that in any and all EDA upgrades". I am myself an EDA developer for a long time, and this is simply not true.



at 7/18/2006 11:36:30 AM, Joe Sawicki said:
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at 7/19/2006 10:01:23 PM, Developer said:
Mike,

I see your point and I admit I reacted in a knee-jerk fashion. In general,from editors like You and John Cooley I expect less exaggeration and more real data. The newsletter from EDA companies are already, pretty good at exaggeration!!!

Another comment, which is all marketing and no truth is "The company cites benchmarks that indicate the parallel architecture offers run times that increase in a linear fashion with the size of the design". If the run time scales linearly with design size, that means all of their algorithms that process the design, have linear time-complexity. I am not sure if any EDA algorithm runs in *linear fashion*.

-Developer (who does not work for mentor)



at 7/28/2006 12:51:13 PM, Mr Brightside said:
I disagree... if you look at the global problem for things like placement, etc they are not linear, right. But if you apply a hueristic to it and can linearize it over a small subset, than that is the same thing. Divide and conquer.

Take PNR. If you place a design flat, ya it doesn't grow linearly. But if you partition it and run the partitions in parallel then you can get linear growth by running all partitions in parallel and then just dealing with the corner cases. This is something we've all been doing for years with a hierarchical design style. Taking a chip and PNRing it as a group of spacially diverse blocks greatly speeds up runtime as you don't get hit by the high end "non linear" growth problem.

DRC is the same way, even better, as the interactions are not nearly as nasty as placement... the partitioning is done for you, just do it spacially if you want (or if you are smarter spacially across hierarchy). The only corner cases are halo rules (for example, metal density) at the boundaries.

Yes, at some point you get diminishing returns, but DRC has been shown to be able to scale fairly nicely (see my post at ESNUG) if implemented properly. Ya, it might not scale linearly to 1000 CPU, but if you look at the subset of what people might want to run, then its "damned near linear". Plus, at some point do you want to add 100 more CPUs to go from 30 minutes to 15 minutes?




at 4/22/2007 5:52:35 PM, Alex said:
Thank You

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