Between The Lines

May 30 2007 9:18AM | Permalink | Email this | Comments (0) |
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Hey folks, in addition to a plethora of new tools and resources at DAC, there will also be two really cool books released at the show. The first was penned by a group of folks at Synopsys and ARM on low power design techniques and the other is on high speed design techniques by high speed systems gurus Lee Ritchey and John Zasio. In a previous blog post, I also wrote about Kurt Keutzer's upcomming book on low power design.

Synopsys fellow Michael Keating contributed a great deal to my May 24 cover story on low power techniques but kept it quiet that he and his co-authors (Synopsys’ Alan Gibbons and Kaijian Shi and ARM’s David Flyn, Robert Aitkin) had an upcoming book on the subject, entitled “Low Power Methodology Manual For System on Chip Design,” available from Springer.

Keating, who also penned the popular “Reuse Methodology Manual” a few years ago, says the book is meant to be a practical guide to low power design, as mainstream designers start to embark on 65nm and 45nm design and must face the ugly issues of low power design…whether they want to or not.

While the book goes over common techniques like clock gating, gate level power optimization, multi-VDD, and multi-threshold logic, it goes into great detail on the newer techniques of power gating and voltage and frequency scaling. “Techniques like clock gating and use of multi-VDD have been around for a while but power gating and voltage scaling are new techniques where folks can see great gains,’ says Keating.

True to its description as a manual, the book guides readers through implementing these techniques. I’ll be moderating a panel session at the official book release at DAC on Wednesday June 6^th.

Here is the Preface to the book:

The Low Power Methodology Manual is the outcome of a decade-long collaboration between ARM and Synopsys commercially and the two of us personally. In 1997 ARM and Synopsys worked together to develop a synthesizable ARM7 core. Dave was the ARM lead on the project; Mike’s team executed the Synopsys side of the project. This led to a similar project on the ARM9.

Shortly after these projects, the two of us embarked on a series of technology demonstration projects. We both felt that we needed to use our products as our customers do in order to understand how to make these products better. So we developed a test chip that combined ARM and Synopsys IP and took it through to silicon. We did the RTL design and verification personally, and borrowed resources to do the implementation.

The experience was incredibly illuminating, and we hope it contributed to improving the IP and tools from both companies.

We quickly realized that low power was one of the key concerns of our customers, and SoC designers in general. So we followed our initial project with several low power technology demonstration projects. The final project was the SALT (Synopsys ARM Low-power Technology demonstrator) project, for which we received working silicon late last year. These projects explored clock gating, multi-voltage, dynamic voltage scaling, and power gating. In all these projects we found that there is no substitute for direct first-hand experience doing low-power IP-based designs. We learned, in the most concrete way possible, exactly what our customers go through on an SoC design.

For years we have been talking about writing a book on low power design. With our experience on the SALT project, our work with customers on low power designs, and our participation in developing the UPF low-power standard, we feel that we are finally in a position to publish our insights and perspectives.

In doing so, we have enlisted the aid of our co-authors. The two of us are primarily front-end engineers, with a background in system architecture and RTL design.

Kaijian and Rob bring a great depth of technical expertise in the physical and circuit design aspects of low power. Alan has developed low power flows for the ARM processors and did the implementation of SALT. As a result, he brings a unique perspective on the implementation issues in low power design.

We cannot overstate the contribution of our co-authors. Without their insights and expertise - as well as the material they contributed directly - this book could not have been written. Like all our joint projects, this book was partly a formal joint project of the two companies and partly (perhaps mostly) driven by the personal commitment of the authors, aided and abetted by many others. We got considerable help from many people for whom this was not part of their job description. These kind souls took time out of their busy schedules, including evenings and weekends, to help us at every step of our journey, from the first joint chip development to the completion of this book. They helped in the architecture, design and tape out of test chips, the building and debugging of boards, and the review and editing of the final manuscript.

It is impossible to list them all, but we list some of the many who contributed to this effort: Anwar Awad, John Biggs, Pin-Hung Chen, Sachin Rai, David Howard, and Sachin Idgunji.

We would also like to thank the staffs of TSMC and UMC for fabricating the technology demonstrators and enabling us to derive the results referenced in the worked examples.

The other cool book that will be making its official debut at DAC is Lee Ritchey’s 2^nd Volume of “Right the First Time: a practical handbook on high speed PCB and system design.” Volume 1 was a big success and served as a practical text for Ritchey's high speed design courses, which he offers via a UC Berkeley extension program and conferences.

In Volume 2, Ritchey goes into great detail on PCB manufacturing, materials, high speed design techniques and tools. The book features some great illustrations and examples. Chapters include The PCB Design Process, Power Delivery Details, PCB Fabrication, PCB Material, Signal Integrity and PCB Structures, EMI and EMC, BG/S and Higher Signaling, Simulation and Simulators and last but not least, Ritchey’s buddy John Zasio, contributed a chapter on Integrated Circuit Package Design.

The book is self published and available via Lee’s website.