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Tuesday, January 30, 2007
SunaptiCAD VeriLogger Extreme: Verilog 2001 simulator provides faster RTL and gate-level simulations
Jan 30 2007 12:54PM | Permalink | Email this | Comments (5) |
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Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing information. Verilogger Extreme claims eight-times-faster RTL simulation and 30-times-faster gate-level simulation than VeriLogger Pro. The simulator supports design libraries and design flows for all major ASIC and FPGA vendors and comes bundled with the vendor’s BugHunter Pro graphical Verilog/VHDL integrated development environment. Suiting low-memory usage, the product allows large designs to run on memory-constrained laptops. VeriLogger Extreme is available on Linux, Solaris, and Windows; a perpetual license costs $4000 on Windows, with a 24% discount through March 2007. Current Verilogger Pro customers with maintenance contracts can upgrade for free.
SynaptiCAD, www.syncad.com
Reader Comments
at 4/12/2007 5:46:03 AM, veriviz said:
Hi, Visual verification of small modules for beginers. Check out this tool to give graphical view of your verilog code vlsi.cs.iitm.ernet.in/veriviz/index.html, it is a totally new approach. Regards
at 6/20/2007 7:15:14 AM, ayaz said:
qqw
at 6/20/2007 7:16:10 AM, ayaz said:
Verliog Programing
at 6/20/2007 7:17:34 AM, ayaz said:
send me code for 8 channel 12 bit ADC at ayaz_qau@hotmail.com
at 6/20/2007 7:18:41 AM, ayaz said:
send me verilog code for 8 channel 12 bit ADC at ayaz_qau@hotmail.com
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