EDN Executive Editor Ron Wilson explores how IC design teams really work: the struggle for power efficiency and performance, wrestling with semiconductor processes and design methodologies, the challenges of global design teams. How do we somehow herd architecture, IP, design and verification into a successful tape-out?
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Profile
Recent Posts
- Intel's Borkar hints at future of SoC architecture and semiconductor test
- ITC panel highlights pioneering work of Stanford Center for Reliable Computing
- Altera Cyclone IV parts signal direction of the global-recession industry
- Gennum offers a study in leading-edge mixed-signal design
- PMC-Sierra takes aim at carrier Ethernet with a new OTN chip
- IDT starts to line up products behind Serial RapidIO Gen2
- Synopsys introduces Matlab-to-RTL synthesis path for datapaths
- Virage absorbs a key piece of NXP: signs for the future of IP?
- Designing for SoI with a standard flow, continued
- ARM 1176 in IBM SoI process demonstrates a cell-based flow
Recent Comments
- Priortaltelia on 3D interconnect session brings new topic to IITC
- birendra singh on Fujitsu launches USB 3.0 SATA bridge chip for PC external storage devices
- Polprav on EDA revenues head downhill faster ... but wait!
- His_wife80 on Boeing postpones test flights again: how's your tape-out looking?
- No_limits82 on ARM 1176 in IBM SoI process demonstrates a cell-based flow
Most Commented On
- India's $20 laptop plan challenges our thinking about system design (65)
- A solar-panel glut could be a golden opportunity (48)
- Why the layoffs if we're still profitable? (43)
- The Tata People's Car may come to North America (36)
- Heard at Hot Chips: As design outsourcing matures, a potential problem is emerging (33)
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