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Recent Posts

• Arteris expands their approach to Networks on Chips
• Intel's Borkar hints at future of SoC architecture and semiconductor test
• ITC panel highlights pioneering work of Stanford Center for Reliable Computing
• Altera Cyclone IV parts signal direction of the global-recession industry
• Gennum offers a study in leading-edge mixed-signal design
• PMC-Sierra takes aim at carrier Ethernet with a new OTN chip
• IDT starts to line up products behind Serial RapidIO Gen2
• Synopsys introduces Matlab-to-RTL synthesis path for datapaths
• Virage absorbs a key piece of NXP: signs for the future of IP?
• Designing for SoI with a standard flow, continued

Recent Comments

• David Stratman (Silistix Dir Prod. Mktg) on Arteris expands their approach to Networks on Chips
• dc207 on Synopsys introduces Matlab-to-RTL synthesis path for datapaths
• Stellar Data recovery on Fujitsu launches USB 3.0 SATA bridge chip for PC external storage devices
• Priortaltelia on 3D interconnect session brings new topic to IITC
• birendra singh on Fujitsu launches USB 3.0 SATA bridge chip for PC external storage devices

Most Commented On

• India's $20 laptop plan challenges our thinking about system design (65)
• A solar-panel glut could be a golden opportunity (48)
• Why the layoffs if we're still profitable? (43)
• The Tata People's Car may come to North America (36)
• Heard at Hot Chips: As design outsourcing matures, a potential problem is emerging (33)

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