Practical Chip Design

Following an active panel on DDR3 DRAM, last week's Denali Memcon offered up a second panel topic: low-power memory design. That's a wide enough topic to allow for a range of discussions, and the panelists--Mostafa Abdulla of Numonyx, Roger Isaac of Silicon Image, Areski Maklouf from ST-Ericsson, and Howard Sussman of Etron—ranged all over it.

In opening statements, Maklouf said that LPDDR is a major issue for the platform architect. "Architects must work with memory providers to find a good solution," he said. Moving in a different direction, Isaac pointed out that no matter how cleverly you architected it, LPDDR was not going to make it for much longer. "We can get 3.2 GB/s per chip out of LPDDR2," he said, "but for the next generation of handsets, w...Read More

One sure indication that low-power FPGAs are beginning to penetrate the domain of small ASICs in power-constrained applications is that the FPGA vendors are running headlong into new design requirements. That proof is reflected in the announcement this morning of a new Cyclone III line—the Cyclone III LS—from Altera. The mid-sized FPGA features low power consumption, plus two feature sets rather novel for Altera: design-protection to prevent reverse-engineering from discovering the programming data, and hardware-level isolation within the logic array to allow for both data security and hardware redundancy.

The low-power credentials of the part are notable for an SRAM-based device. Altera manager of product marketing Umar Mughal said the chip dissipated less than a quarter Watt of static power, primarily through use of TSMC's 60L low-leakage process. That proc...Read More

Many—maybe even most—SoC design teams use C or C++ to explore algorithms and the behavior of their system before they begin implementation. That makes it entirely natural for designers of new blocks—as opposed to those who are importing previously-used IP at RT level—to wish there were a way of synthesizing the C code directly into RTL to insert it into their implementation flow. After all, much of this behavioral C will get incorporated into testbenches for the verification team, so why not capture the design behavior as well?

In fact for some types of blocks, many teams already to this today. A number of tools will synthesize signal-processing datapaths from a carefully-written C description of the algorithm into a very serviceable RTL description of the necessary hardware. In some applications, such as wireless baseband signal processing, these...Read More

LSI officially launched a new era in disk read-channel technology this week with the RC9500: a new generation mixed-signal read channel intellectual property (IP) core cluster. The block, intended for integration with a drive vendor's IP to create a single-chip drive electronics subsystem, plants two milestones at once. The IP is LSI's—and possibly the industry's—first adventure into 40 nm. And it appears also to be the first application of a low-density parity-check (LDPC) algorithm in read channel products. LSI intends the IP for the coming generation of 500 GB/disk 2.5-inch, and 1 TB/disk 3.5-inch drives.

The 40 nm part is pretty self-explanatory. LSI director of product marketing Gordon Paulus said that the technology allows the read channel to reach 4 Gb/s within the power budget customers hav...Read More

Solido Design has, as previously projected, added another tool to their Variation Designer platform. Well-Proximity is the first tool in a second package that runs on the Variation Designer Platform, complementing the Statistics package.

The well-proximity issue, according to Solido corporate applications engineering manager Kristopher Breen, becomes an important source of process variations at 90 nm. But to date, most design teams have either been ignoring the effect—risking significant yield loss or outright design failures in their analog and custom circuits—or they have been inserting guard-band spacing around the edges of well implants, trading die area for safety.

The mechanism th...Read More

The problem of memory power management in an SoC has two components. First, the hardware hooks must be available to perform clock-gating, voltage reduction, and power-gating in order to attack both dynamic and static power consumption. But second, and just as important, the memory instance must be told when it is allowable to use its various power-saving modes. This is a non-trivial problem because many modes that go beyond simple clock-gating have significant entry-exit latencies and actually increase dynamic power during the entry and exit process. So without foreknowledge of circuit activity, it's neither safe nor rewarding to use these modes.

The result is often that designers, lacking detailed constraint data about memory use, tend to get conservative. They will only clock-gate the memory when the inputs can't change, and they often will use more aggressive power-do...Read More

Time was when high-speed clock generation was about supplying clock signals to CPUs. But with the proliferation of graphics hardware, high-speed I/O, and RF in everything from handsets to server farms, the CPU has ceased to be the only important market for fast clock generators. If fact the whole PC industry may be in the shadow of networking, enterprise computing, and consumer electronics in this regard.

But these broader markets have their own needs in addition to the obvious cost and power constraints. These applications need a vast array of different frequencies, differing degrees of jitter control, and in some cases frequency-spreading and other interesting features. In recent days both Cypress Semiconductor, one of the pioneers in programmable clock generators, and Cypress spin-off SpectraLinear have introduced new families of clock chips. The two have started with...Read More

An interesting thread of reasoning emerged at several different spots during the Research@Intel Day yesterday. The thread started with a passing mention, during CTO Justin Rattner's introductory remarks, of the substantial reduction in static power in the Moorestown CPU architecture. According to the CPU architect Rattner summoned to comment on the claim, this was achieved primarily by extensive use of power gating in the CPU.

But power gating is not a magic spell. It only works under the right conditions. Specifically, for power gating to actually save energy, the CPU has to know in advance when it will be able to shut down a section of the hardware for a considerable period of time. Otherwise, not only will the latency required to re-power the block interfere with processor timing, but the energy consumed in saving state, isolating the block, powering down, and reversin...Read More

The event of interest in Silicon Valley this morning was the annual Research@Intel Day, in which the various research teams at Intel's ten R/D centers around the world get to do Show and Tell for the press. There's much to ponder about the event, but first I should focus on an invited guest who is not, strictly speaking, part of the Intel Corporate Technology Group. Mike Mayberry, vice president of the Technology and Manufacturing Group, describes the distinction between his organization and what's now called Intel Labs as follows: "Technology and Manufacturing does the process R/D and runs all the Intel manufacturing facilities. Intel Labs' job is to figure out what we should build, and how users would live with it if we did."

Despite the organizational difference, Mayberry was at the event this morning hosting a round-table discussion on manufacturing researc...Read More

The private debate continues among process engineers as to what will be the gate stack of the future. Intel seems to have already committed to a high-k, metal-gate path. TSMC has been publicly resolute in sticking with silicon oxy-nitride dielectrics and poly gate electrodes. Other vendors are investigating many options. But about the only public visibility of this private debate comes from the occasional paper to surface at a technical conference.

This week is bringing quite a bounty of such papers, from the VLSI Technology and Circuits Symposium in Kyoto. Two gleanings from the bounty suggest two remarkably different data points—although at two very different process nodes—for the search for the golden gate stack.

In ...Read More

One of the big differences between DisplayPort and other display interfaces, such as HDMI or DVI, is that the latter transmit video data as continuous bit streams, while DisplayPort transmits the data in packets and allows for asymmetric two-way transfers. If your application is simply connecting a graphics chip to a display, packetizing creates a lot of overhead for little real benefit. But if you are driving multiple displays, there are some advantages to all that extra work.

Now personally, I can't imagine wanting multiple displays. But if you are an investment or commodities trader, for instance, you need as many displays as possible to show your boss that you are working hard enough to justify your seven-digit bonus. More realistically, if you are a chip designer or mechanical engineer who has to multitask as a matter of routine, you actually do need multiple display...Read More

The focus among the big three in the EDA world seems to have shifted a bit of late: from developing new point tools to integrating existing tools into interoperable platforms. Nowhere is this more necessary than at the electronic systems level, where design teams' skepticism about the whole concept tends to be met with a blizzard of unrelated point tools with differing metaphors, user interfaces, and data formats. It's enough to keep a design manager skeptical.

"The real world today," said Synopsys product director Frank Schirrmeister, "is that a systems-level designer has to work with models from different vendors, different simulation platforms, different software debuggers, drivers from different sources, different vendors of transaction-level models, and different sources of protocol stacks. You can end up dealing with five or ten EDA vendors, two or th...Read More

PCI Express gen-3, the 8 Gbit/s next generation of the successful serial bus standard, is still working its way through the definition process. It is now at revision 0.5. But already there is a rush to market, even though nothing is really finalized. Today Gennum's Snowbush IP division announced release of a 4-lane gen-3 PHY and accompanying endpoint/root/dual-mode controller block. The two IP blocks are available as GDS-II and RTL, respectively. The current implementation of the PHY is designed for TSMC's 40 G process.

Accompanying the Snowbush announcement, interface-chip specialist PLX Technology announced that they are using said IP in what is apparently the first gen-3 switch chip. So the vendors are off an running, before the standard...Read More

In a remarkably short arc, Zigbee radios for embedded applications have gone from "how are you gonna do that in CMOS?" to commodity items. "In theory, these days the Zigbee radio is just another peripheral in an integrated embedded system like a power meter," observed Ember senior vice president of engineering Skip Ashton. "The radios have all been converging lately onto pretty similar sets of specifications."

Still, that's not quite the whole picture. When you integrate a Zigbee radio onto a microcontroller, Ashton points out, this one peripheral takes up about a third of the die. And it requires special design skills way beyond those necessary for counters, timers, or A/D converters. The size, power consumption, and proprietary skills that go into a Zigbee radio continue to make it a special interface, somehow not quite commodity.

An...Read More

For the most part analog designers have avoided the issues of sub-wavelength design-for-manufacturing (DfM.) Most chips with primarily analog content are done in large geometries—180 nm or larger—where issues such as lithography optimization, metal-density and pitch rules, and well-proximity effects are non-issues. Even when analog designers work on advanced-geometry SoCs, the tend to use very relaxed dimensions on analog circuitry, avoiding the need to worry about DfM.

But all that is changing, according to Tom Wong, vice president of business development at DfM tool vendor Takumi Technology. A combination of factors is pushing analog designers inexorably toward smaller geometries, and into the waiting jaws of DfM troubles. And unlike in purely digital designs, where the penalty f...Read More