Practical Chip Design

Intel's Ken Tallo has taken up the chairman's baton at the Open SystemC Initiative, the organization that drives adoption, infrastructure, and support for SystemC. Speaking with Tallo yesterday, we had a glimpse into one insider's view of the future of the organization, the language, and to some degree, the whole technology of system-level behavioral modeling.

At one level, Tallo's aspirations are what would be expected of any incoming chairman: increase membership, improve the quality of the organization's functions, and strengthen relationships with allied organizations. But once we moved from generalities to specifics, Tallo's view of the system modeling world became quite fascinating.

Let's start with broad...Read More

In an uncharacteristically non-integrated-circuit keynote topic, the Hot Chips conference this week offered up Dick Swanson, co-founder, president and chief technical officer of SunPower, to give a brief history of the company. Along the way Swanson outlined the technical evolution that brought the company from, more or less literally, the middle of the desert to a rooftop near you, and may well take it back again. And he gave some examples of the kind of numbers-bending hype that is gradually raising suspicions about the entire sector.

In 1985 SunPower spun out of Stanford University, according to Swanson, convinced that silicon wafer-based solar cells could never be competitive on cost and that the future lay with concentrator technology, in which a large amoun...Read More

The Hot Interconnects session yesterday that explored photonic alternatives to interconnect for many-core processors and SoCs also produced a paper that approached the same problem from an entirely different direction: a blend of conventional routing and fast global electrical lines to create an hybrid NoC (network on chip.)

The paper, a joint product of researchers at Princeton, Oregon State University, and the University of Texas, Austin, began with the argument that there are two fundamentally different classes of problems in establishing a NoC for chips with large numbers of cores. One class of problems involves moving the very large data streams that might traverse such chips—the data plane problem. The other involves the low-latency, short transactions nec...Read More

The lead-off session at the undeservedly little-attended Hot Interconnects conference at Stanford this morning examined the growing challenge on chip interconnect technology as today's small-scale multicore processors evolve into chips with tens or hundreds of processor cores. Papers examined two primary issues: the increased need for on-chip bandwidth between processors and memory instances, and the need for bandwidth between the chip and external DRAM, the latter on the assumption that memory hierarchies may come and go, but DRAM will be with us forever.

The papers all emphasized the same overriding issue: power. For projections say that we will run out of power to drive the interconnect, and capacity to cool it, before we run out of physical area for laying out more wires. Interestingly enough, three papers came to the same conclusio...Read More

Yesterday evening's Hot Chips panel, Ready, Fire, Aim: 20 years of hits and misses at Hot Chips, managed to include some sage business advice along with its architectural observations. After all, many of the panelists had been in pioneering CPU projects or start-up companies themselves.

One useful insight offered by several of the panelists was to not waste someone else's money—or, in any case, your own—by basing a product position on a technology other than CMOS. Howard Sachs, who has a long history of experimenting with CPUs in arcane technologies, gave an obituary page full of great ideas that relied on ECL, CML, or GaAs for their performance edge. Invariably, he pointed out, design delays, yield problems, and issues with enormous heat generation delayed production of the design j...Read More

You might imagine that somewhere in a back room at conferences the old hands at microprocessor architecture get together over dinner and a few bottles of wine--the sort that must be concealed in expense reports--lean back in their chairs, and talk long into the night about lessons learned and lessons repeated. Last night the minority of Hot Chips attendees who stayed around after dinner had the privilege of listening in on just such a discussion, staged as a panel.

And an august group is it was. Chaired by Nick Tredennick, who has been in microprocessor design since the Motorola 68000 development, the panel included Insight 64 analyst Nathan Brookwood, Intel vice president and low-power processor pioneer Dave Ditzel, Techvision principal and MIPS pioneer John Mashey, the legendary Berkeley professor and RISC champio...Read More

There has been much angst about design outsourcing in recent years, the majority of which has come from US-based designers who have lost, or who fear for, their jobs. But as the industry gets more experience with the practice, there are other problems emerging as well, that impact not just designers but the outcome of designs, and quite possibly the competitiveness of the companies that outsourced the work in the first place. This is due to a natural evolution in the progress of outsourcing.

All of this came from an overheard conversation at Hot Chips this afternoon. A senior architect for a major US company was talking about the problems he has faced with outsourcing. He was describing how as the design teams on the other side of the Pacific get more sophisticated, the partition between the US and the—usually...Read More

The Monday keynote at Hot Chips this year was in the very capable hands of Sebastain Thrun, Stanford University professor of computer science and electrical engineering, director of the Artificial Intelligence Lab, and not coincidentally, leader of the Stanford teams in the DARPA Challenges. He described the control system architecture that has enabled three generations of autonomous vehicles to complete these events, winning first place in the Grand Challenge and second place in the Urban Challenge.

Thrun's story started with a series of failures. The original idea for the Grand Challenge, Thrun said, came from a US Defense Department frustrated that enormous sums of R/D money invested in the traditional military contractor network had failed to produce a useful au...Read More

System-in-Package design has been growing up in a no-mans land. SiPs require circuit design, simulation, routing, extraction, and closure, just like ICs or PCBs. But neither the tools from the chip design world nor the traditional PCB tools are really appropriate to the problems of SiP designers. On the principle that every missing link is a business opportunity, Cadence announced today that it is providing significant support for SiP design, along with significant strengthening of its support for high-density, high-speed PCBs, in its Allegro 16.2 release.

There are new features, based on Cadence's assessment of the problems of the SiP designer. Paramount among the challenges, obviously, is that the spacing used in SiPs—both internally and at the interface to the board—are well into the land of high-d...Read More

Just to add some balance to my previous posting about the future of FPGAs, I thought I should introduce a little corrective reality. In a recent conversation with Pratul Shroff, president and CEO of design house eInfochips, the subject of FPGAs came up. Shroff said that in his business, he saw systems houses moving away from ASICs to FPGAs. "The costs of doing an ASIC have simply become too high for many designs," he explained. So in areas such as broadcast equipment, surveillance, and health care, Shroff has seen large FPGAs displacing medium-sized ASICs.

This has not been an easy transition, though. Shroff said that as the largest FPGAs—the only ones that can offer SoC-like logic and memory density—come into use, placement and routing are ...Read More

As the growth in video sources, video storage media, and video display devices continues, we are rapidly replicating the Tower of Babel. Video data formats, compressed data formats, transport containers, decompression algorithms, and—maybe most critically—error recovery algorithms are all appearing like fruit flies above an over-ripe peach on a hot August afternoon.

One of the results of this proliferation is that the specifications for boxes that have to sit in the midst of the delivery channel from content creation to production to head-end to consumer are beginning to sound like the specs for a Star Trek universal translator, or perhaps more accurately, like the description of Douglas Adams's Babel Fish. All you have to do is accept packets of containerized video in whatever format, somehow get at the video, convert it into whatever format the client requi...Read More

There is a long-standing debate in the industry over the future of FPGAs. The FPGA vendors have argued for years that their destiny is to replace ASICs as the way most digital systems are implemented. And in fact ASIC design starts have been falling for several years, as FPGA design starts have continued to rise, although these two numbers actually mean quite different things, making even a relative comparison murky.

But skeptics have pointed out that FPGAs themselves are vulnerable to replacement. ASIC vendors argue that they have not been losing design starts to FPGAs—they have simply been moving up-market, into the large SoC and mixed-signal designs of which FPGAs are incapable, hampered as the FPGAs are by limited density and performance, relatively high power consumption, and lack—with ...Read More

Moving from a single-port to a dual-port PHY doesn't sound like a big project, particularly if it's done by moving to a more advanced process. But the in the world of 10GBASE-T physical-layer chips, where the name of the game is achieving impossible data rates over twisted pairs, nothing can be as easy as it sounds. (For some background on the standard, see here.) Today's introduction from Teranetics makes a good case study.

Teranetics introduced their single-chip PHY some time ago as a 130 nm CMOS design. Today's dual-port part is a 65 nm CMOS design. That in itself sounds like it pretty much explains the design process, except perhaps for the signal-integrity checks. Smaller circuitry, so you can put two on one die.

But that would be a vast over...Read More

About this time last year, we explored the creation of NXP—the company formed when private equity players purchased Philips Semiconductors. At that time we left some questions open about how the very long-term business of generating revenue from the underlying technology value of a semiconductor company would fit with the borrow-and-flip tendencies of the private equity world. Not surprisingly, NXP's management assured us, then and since, that private equity money was patient money: that in fact the investors were encouraging NXP management to embark on a growth-through-acquisition strategy, not a cost-cutting strategy.

Not surprisingly, times have changed. Perhaps it is that the collapse of the global credit markets at which the private equity companies fed at will has left them a little short-t...Read More

A snide person might observe that if circuit designers were equipped with the same formidable mathematical skills as economists, we would all be using single-ended triode amplifiers that oscillated when we turned the gain up. (As it is, only the very rich get to use these, but that's another rant altogether.)

In my local newspaper this morning was an article reporting that the housing market was in "a tailspin" with no hope in sight. I suppose that the implication was that if you don't own your home outright, you'd just as well pack up and move to an apartment now and waste no more money on mortgage payments.

Unfortunately for the reporter's premise, he or she published along with the article a graph of housing prices vs. time. It showed a slightly-damped cosine wave—the sort of time-domain response you would expect if you hit a slightly under-damp...Read More