Practical Chip Design

In a plenary talk at the International Test Conference this morning Intel fellow Shekhar Borkar offered a tightly-reasoned description of how IC architectures will look in a few years, with some observations about the future these architectures imply for test engineers. The talk certainly represented the views of Intel's director of microprocessor technology, and may indicate the general direction of thinking within the company.

Starting with the familiar, Borkar discussed just what kind of chip one could build today, and tomorrow, with a power budget of 65W. Today, he said, you could combine about 50M logic gates with about 6 MB of cache: a typical dual-core high-end CPU chip. But ten years from now, Borkar warned, scaling in both energy-efficiency and delay will have slowed down considerably, while the magnitude of process vari...Read More

An evening panel session at the International Test Conference this evening reviewed decades of the research work at Stanford University's Center for Reliable Computing, and nearly turned into an encomium for one man: the Center's director, Ed McCluskey. By offering statements from many CRC members past and present, the panel showed the remarkable range of technology vital to the industry in which CRC—and McCluskey—have played a seminal role.

In the early days, according to the first panelists--including Dan Siewiorek, who spoke by pre-recorded video--the center stayed close to the implications of its name, doing original work on such topics as fault-tolerant computing circuits, triple module redundancy, ...Read More

It's not often that a simple product-line extension makes it over the threshold into newsworthiness here. Generally anyone who is interested can put a ruler on the product line chart for a chip family and pretty much figure out the data sheets for any new members of the family. That could probably be said as well for Altera's Cyclone IV GX and Cyclone IV E FPGAs, which Altera announced this morning. But in a world where standard-product IC developers must look quarters ahead and try to read the odds for emerging market opportunities, a couple of chip announcements might tell us something about where the semiconductor industry is going.

The technical story on the two new product lines is pretty straightforward. Both families are build on TSMC's 60 LP process, the same low-leakage, moderate-speed process Altera used for the Cyclone III LS family in 2007. The logic array arc...Read More

Gennum, the generally quiet high-performance mixed-signal chip and IP vendor, is rapidly spreading its customer base across a wide range of applications. Recent announcements have covered a single-chip 10 Gbit/s EPON transceiver, an Advanced Video Interface for Industrial Applications (Aviia) receiver, and a PCI Express 3.0 PHY IP block, the latter recently selected for use at Cray Inc.

The applications and the specific circuit designs are quite different. The Aviia receiver, for example, depends on a combination of analog and digital equalization techniques to bring the physical plant of TV broadcast studios—entailing runs of up to 150m of Belden 1694a co-ax—up to 3 Gbits/s to handle 1080p/60Hz signals. In contrast, the EPON transceiver exploits high-speed clockless CDR (clock-data recov...Read More

PMC-Sierra continues to be very positive on the gradual spread of the ITU-T G.709 Optical Transport Network (OTN.) The company sees OTN dominating the long-haul and Metro links that make up the invisible muscle and bone of the Internet. But PMC also expects an even further evolution: OTN from enterprise data centers and access routers, digital subscriber-line access multiplexers (DSLAMs), and wireless backhaul connections into the carrier Ethernet Switch and router (CESR) boxes.

"There is an opportunity for carriers to realize significant savings in operating expenses by spreading OTN across their equipment," said PCM director of marketing Babak Samimi. "OTN offers an environment optimized for mixed modes of packet traffic with a single, unified network management layer all the way through CESRs and even out to DSLA...Read More

The ordinary life cycle for a proprietary I/O scheme begins with its creation to solve a specific design problem. If the product becomes widely used, the interface may get embedded in an application space and become a de-facto standard, remaining until it grows unserviceably obsolete. But if the vendor behind the spec is powerful enough, the bus may survive and evolve, gaining performance and features to support new generations of needs. For examples, consider the evolution of PCI into PCI Express gen-X, or, for our purposes here, the course of RapidIO.

You can trace the inception of RapidIO to the point at which DSP designers realized that they had painted themselves into a bandwidth corner by thinking of DSP cores as chips rather than as IP. But the basic concept of a packet-switched network based o...Read More

Leveraging high-level synthesis technology developed at Synplicity, Synopsys this week introduced a unique approach for generating synthesizable datapath RTL from algorithm descriptions in the Matlab environment. Unlike other high-level synthesis tools, which start with a system description in SystemC or another C dialect, Synopsys's Synphony tool starts with the native scripting language of Mathworks Matlab, M-files. Synopsys refers to this mathematics-like scripting as the M Language, which is not to be confused with the M (or MUMPS) language used to develop database applications.

Synphony offers a two-step conversion process. After algorithm designers have explored and verified their algorithm in Matlab's implicitly real-number space, Synphony converts the model to fixed-point using a tool called M-Compiler. This automatic conversion step bypasses what would ordinaril...Read More

In a startling move announced this morning, growing semiconductor intellectual property vendor Virage Logic announced that, through an unusual and complex agreement, it has in effect acquired much of the technological heart of NXP Semiconductors. The agreement, billed by the two companies as a strategic alliance, cannot but bring profound change to both organizations.

Under the agreement NXP will transfer about 160 employees, with their associated assets, IP, roughly 25 families of patents, and four years' of cash payments totaling $60 million, to Virage. In exchange, Virage will give NXP 2.5 million shares of common stock, valued at today's closing at about $15M, will con...Read More

In the just-previous post we discussed ARM's implementation of an ARM 1176 core in IBM 45nm SoI using a standard CMOS flow. Now we should continue coverage of this sessions at this week's IEEE International SoI Conference to discuss how that is possible.

In most respects, the differences between bulk and SoI are irrelevant to a cell-based design flow. If the cells are designed correctly and accurately characterized, then to the tools they are just ordinary standard cells, according to Synopsys's Kevin Kranen. But Kranen pointed out two important exceptions to this generalization, and Michael Jacobs of Cadence elaborated on a third. All three relate to the behavior of the notorious floating-body transistor in the SoI process.

In SoI, remember, the transistors live in a...Read More

For several years it has been clear that SoI processes have a more favorable speed vs. voltage characteristic than comparable-node bulk silicon processes. This advantage can mean either lower operating voltage at a given speed---and thus lower power—or higher performance at a given voltage. And the presence of vast quantities of both the Xbox 360 and the PlayStation-3 should eliminate any question about volume manufacture, at least from IBM. So why is SoI still so rarely used?

The normal answer is the lack of design infrastructure. Early on, most SoI designs were at the high-performance fringe, and so people rightly associated SoI with custom design and highly-skilled teams. It would require new device models, new libraries, and new tools to make SoI work in a normal cell-based RTL flow, this reasoning said.

But three papers at the IEEE International SoI Con...Read More

Ensphere Solutions, a design-services shop that has recently entered the fabless semiconductor market with a range of multi-Gbit optical transceiver chips, today became one of the first vendors to announce hardware in support of Light Peak, Intel's vision of a single optical interconnect cable for PCs and mobile devices. Ensphere is now sampling a 10 Gbit, two-channel transceiver die for use in the optical modules in a Light Peak connection.

In terms of core functionality the transceiver is fundamentally no different from other 10 Gbit transceivers, according to company vice president of marketing Al Gharakhanian. The die includes a VCSEL driver, a transimpedance amplifier for the PIN diode output, and a differential interface to the outside electronic world. While no 10 Gbit transceiver is a tri...Read More

Boeing--giant aircraft manufacturer, equally giant but much lower-profile defense contractor, and one-time paragon of complex project management--has hit the newspapers twice in recent weeks in the worst possible way. The company has announced that it is taking financial charges because its two premier commercial projects—the 787 Dreamliner and the 747-8 cargo version—are both delayed, again. Neither will meet its most recent schedule for first test flight. This is a direct concern for suppliers providing electronics into those programs, of course. But it is also a cautionary tale for any chip design team engaged in a complex project.

The sadness of it all is the irony that this should happen to Boeing. In the late 1960s, Boeing pretty much astonished the aircraft industry by creating arguably the world'...Read More

As much time as we spend here discussing the challenges of 40nm or the promises of 28nm, 180 must look like a typo. But in fact two announcements this week clearly show that 180nm processes are alive and well, albeit today as niche offerings rather than mainstream SoC processes. For some designers, 180 is still a geometry to migrate to, not a legacy to migrate from.

There are several possible reasons for looking at 180nm. Maybe the most obvious is that the technology is mature, the equipment is likely to be fully depreciated, and hence the wafers are likely to be cheap. And the mature tools will be affordable as well. If you are doing a moderate-sized design—say, no more than a few million gates—180 may be close to optimum die cost.

Another important reason is precision analog circuitry. A 180nm process, with its 1.8V core supply and ...Read More

In the discussion of Globalfoundries celebrated spin-off from AMD and subsequently-announced intent to purchase Chartered Semiconductor, one question seems basic: do we really need another foundry right now, and if so, why? Or was the whole exercise really just about getting some big assets off of AMD's balance sheet? The answer from customers is yet to be heard. Globalfoundries has announced only one customer so far, ST. But the company is clarifying its strategic positioning, and it clearly does not intend to be just one more foundry.

That position, as you might expect, is built on Globalfoundries' one big customer: AMD's microprocessor division. This one product line means that Globalfoun...Read More

No, that's not a light at the end of the tunnel. The news on EDA revenues in the second quarter is dismal compared to the relative optimism after Q1. But at least the trends in EDA, IP, and design-services revenues are beginning to show some interesting, and possibly informative, patterns.

This morning the EDA Consortium Market Statistics Service reported revenue numbers for the second quarter of 2009, and the over-all picture is not a happy one. Total revenue for the sector is down almost 16 percent compared to the second quarter of 2008, with just over a 14 percent drop in EDA tool revenue, and a rather precipitous 28 percent drop in the much smaller category of services revenue. This drop was much more se...Read More