Practical Chip Design

Gennum, the generally quiet high-performance mixed-signal chip and IP vendor, is rapidly spreading its customer base across a wide range of applications. Recent announcements have covered a single-chip 10 Gbit/s EPON transceiver, an Advanced Video Interface for Industrial Applications (Aviia) receiver, and a PCI Express 3.0 PHY IP block, the latter recently selected for use at Cray Inc.

The applications and the specific circuit designs are quite different. The Aviia receiver, for example, depends on a combination of analog and digital equalization techniques to bring the physical plant of TV broadcast studios—entailing runs of up to 150m of Belden 1694a co-ax—up to 3 Gbits/s to handle 1080p/60Hz signals. In contrast, the EPON transceiver exploits high-speed clockless CDR (clock-data recovery) technology and proprietary laser drivers. But they all spring from a common technology strategy, according to Gennum's senior vice president and general manager for analog/mixed-signal products Martin Rofheart.

At the heart of the company's strategy are skills in two process technologies: SiGe and Silicon CMOS. There is a tight focus on a few key circuits that serve as enabling technologies across a wide range of applications: 10Gbit drivers and receivers, clockless CDRs, and mixed-signal equalizers. And there is a company commitment to maintain the expertise necessary to move these circuits to future process nodes.

"PHYs are going to continue to follow the process migration," Rofheart said. "But as they do, development costs continue to increase. Silicon CMOS in particular requires a tremendous amount of digital compensation as geometries shrink, and even the architectures do not always scale for ever."