Practical Chip Design

Mar 20 2008 5:25PM | Permalink | Email this | Comments (1) |
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A panel discussion at ISQED this week took on a question of considerable importance to design teams who are moving into 90 and 65 nm process nodes: Is DfM helping or hurting? The answers, far from unanimous, shed a lot of light on design at advanced nodes.

The discussion began with definitions. Probably the most comprehensive statement came from the irrepressible Riko Radojcic of Qualcomm, who said "DfM is just a fancy name for process-to-design integration." In more detail, panelists described DfM in varying ways: a set of point tools, an evolving collection of tasks. There was general agreement that this collection of objects had to be brought together, but that this had not been achieved yet. "Today we have an uncoordinated hand-off of manufacturing data to design," said Chartered Semiconductor VP Walter Ng. "Like signal-integrity tools a few years ago, DfM needs to be integrated into the flow."

Opinions also varied as to who should have to pay for DfM. Virage Logic Chief Scientist Yervant Zorian pointed out that who ends up with the bill for DfM can depend on the business model between the design team and the foundry. "If I'm buying wafers from the foundry, I will pay for the DfM. If I'm buying only tested chips, the foundry will pay for it."

More discussion developed over the question of whether DfM was really necessary. "A while ago, the transition from 90 to 65 looked like the end of the world," Radojcic said. "Now, we are confident about designing at 45 nm, and the difference is that these tools have given us some visibility of the manufacturing data."

Cadence corporate VP Richard Brashears agreed with Radojcic that just how DfM presented its value depended on the methodology in use. If a design team is doing extensive custom work, they will use detailed point tools to bring process data into their analysis—and ideally, into their design—processes. If the team is using Restrictive Design Rules, DfM tools may as invisible to the design team as TCAD is now.

Tim Horel, senior director of hardware operations at M2000, put some quantitative data into the discussion. "Yields at 65 nm now can vary by a factor of 2. DfM correctly applied, by a sufficiently-informed designer, does have value." Horel also pointed out that different styles of design would require different tools: TCAD for full-custom designs, and simple pattern-matching tools for typical cell-based ASIC design styles. Thus a single chip design could require several different approaches to DfM in different blocks.

Zorian added that not all DfM is predictive. Some tools, such as self-repair and diagnostic IP for memory structures, are directed at increasing the slope of the yield curve not by making the chip perfect, but by making it robust and diagnosable.

Ng provided the contrary voice here, suggesting that the value of DfM was to some degree a function of the maturity of the process. As processes mature, he argued, the need for DfM decreases. "At 65 nm today, teams that simply use good design practices have high odds of success. If you are doing a bleeding-edge design at 40 nm, that is different."

Ara Markosian, CTO of Ponte Solutions, suggested that as design teams had moved from 65 to 45 nm, DfM had evolved from an option to a part of the flow, not because of a difference in process maturity so much as because the design-dependencies of variations had increased so much that they had to be dealt with. But he worried that the success of DfM tools depended on the accuracy of data from the foundries. That data is very expensive to collect and format for use by the tools, and it can be mined for insights that the foundries might not be anxious to share.

In response to an audience question, the panel discussed the necessary tension between the time it takes for a foundry to collect all that data and transmit it into the tools, versus the need of early adopters to move quickly. Panelists agreed that the tension was real. Ng said "Getting good data means running a representative amount of silicon while we are still turning the knobs on the process. Making this work for customers requires close alignment between our teams and our customers. A number of our early customers have design teams resident in our fabs."

Several panelists said that the delay meant that design teams, tool vendors, and library vendors all had to engage with the foundry far earlier than they had in earlier generations. "IP companies have to engage early—while the process data is still changing," Zorian said. "It leads to some inefficiencies in our work, but it is necessary."

The result, according to Radojcic, is still a net positive. "This is all about yield ramp," he said. "And in fact, our ramp rate at 65 nm has been faster than it was at 130."

Another audience question brought the panel to a discussion of economics, asking if the DfM tools, with their sobering license costs, were simply too expensive for start-ups. Horel replied that when you are a start-up, as M2000 is, "you use your money as best you can. Sometimes that means you rely on design services for some things." Radojcic added that he saw a gradual bifurcation between true fabless semiconductor companies and what he called "integrated fabless manufacturers"—companies that didn't technically own fabs, but had process engineering teams and could work as equals with foundry process engineering groups.

Ng added data. "We are still seeing start-ups working at 45 nm," he said. "But we are also seeing more and more use of small- to mid-sized design services companies to do back-end design. These fabless start-ups depend on architectural differentiation, and let someone with access to the expensive tools and talent do the physical design." There was a worry, he said, that as DfM tools grow more necessary and more expensive, even those mid-sized design services companies might not prove scalable enough to afford them. Then physical design might be absorbed by the foundries, another panelist suggested. Ng said that could happen, but that physical design was not in a foundry's core competencies, and might not be a happy union.

Altogether, the panel offered a view of DfM tools as fragmented, but necessarily headed for integration into advanced flows. They emphasized the vital link between foundry data gathering and the accuracy of the tools. And in discussion, the panelists gave a glimpse of how the inexorably growing need for process data during design—even early in design—was reshaping the industry around us.

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