Practical Chip Design

As anyone who has tried to route a board with a large number of GHz I/Os knows all too well, it would be wonderful to have direct optical interconnect between ICs. The potential bandwidth would be large, the signal integrity issues minimal, and perhaps the power much lower. But there is one huge problem: the technologies necessary to illuminate an optical channel, modulate it and convert the optical signal back into an electrical one are all big, expensive, and incompatible with standard CMOS processes. This is a problem on which Intel researchers have been toiling for some time. And earlier this week, they announced another incremental step toward a complete solution: an avalanche photodetector that is in principle compatible with silicon CMOS processes.

This announcement is one step in a long chain, which began in 2004 with demonstration of a 1 GHz silicon light modulator, and has over the years added faster modulators, silicon waveguides, hybrid laser light sources, and last year a PIN diode 40 GHz detector. At this point, all the pieces are in place for a commercialization effort to produce a 10 Gbit/s optical interconnect system with a range on the order of 5 to 10 meters, according to Intel fellow and director of the Photonics Technology Lab Mario Paniccia.

This speed range is no challenge for discrete optical interconnect, of course. But using conventional technology—which means using III-V materials—the cost per channel would be an order of magnitude higher than for a silicon-CMOS solution, and the chips would have to use multi-die packaging to combine the logic and photonic components.

The detector Paniccia described is a two-layer avalanche device. Strictly speaking, it is not a silicon device, but a Si-Ge fabrication. But since advanced CMOS processes have been using germanium layers for some years now to induce stress in transistor channels, at least most of the integration challenges with Ge have been solved, so it seems fair to say that this device is silicon-CMOS compatible. And Intel has laboratory devices working, so this is not PowerPoint technology.

Functionally, the avalanche detector is a two-layer device. The top layer, exposed to incident infrared light, is germanium, and simply allows incoming photons to create electron-hole pairs in its lattice with high efficiency. Germanium, it turns out, is far better at this job than silicon, given its high absorption at this wavelength. Beneath the germanium layer is a layer of silicon. If you bias the stack, the electrons will migrate into this silicon "multiplication region" with enough energy to create additional electron-hole pairs, which will go on to create further pairs, and so on—hence the term avalanche. The result is a current through the device that is significantly larger than the number of electron-hole pairs directly created in the germanium detector layer, and hence, gain. In an application, of course, gain converts into improved signal/noise ratio, improved range, or some combination of the two.

The device is fabricated as a cylindrical six-layer cake. The top layer is a combined passivation and anti-reflection coating. Immediately below this is a thin P+ germanium contact layer, followed by the micrometer of intrinsic germanium that actually absorbs the photons and spawns the initial electron-hole pairs. Next comes a thin P-type silicon charge layer, followed by the half-micron-thick intrinsic silicon multiplication layer. At the bottom of the stack is an N+ contact layer resting on the substrate.

The real trick, apparently, occurs at the junction. Germanium and silicon have different lattice spacings—that's why strained silicon works. So if you just grow the intrinsic germanium layer on top of the silicon charge layer, you will end up with periodic lattice dislocations, which increase dark current, reducing the SNR. Paniccia would only comment at this point that Intel had "optimized the thermal growth profiles to reduce the impact of the dislocations." One suspects there is a lot of toil behind those words.

According to Paniccia, the combination of germanium for the detector and silicon for the multiplier has a lot going for it. Both materials exist in today's CMOS processes, of course. As mentioned, germanium is an excellent detector medium for infrared. Surprisingly, silicon turns out to be an excellent avalanche medium, with inherently low noise due to the extreme crystalline purity. Paniccia says that the silicon layer actually works better than reported results on III-V materials for multiplication regions.

The bottom line for this experiment is that Intel has demonstrated 40 Gbit/s detection at 95 percent optical efficiency on wavelengths up to 1.56 µm, a whopping 340 GHz gain-bandwidth product, and under 200 nA dark current. It's a long road from here to commercial monolithic ICs with integrated optical interconnect. And in all probability there will always be a little Indium-Phosphide lump sitting on the die somewhere to act as a light source, since silicon doesn't lase. But the pieces are coming together.