Practical Chip Design

Jul 21 2008 12:30PM | Permalink | Email this | Comments (2) |
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Not that long ago it would have been unthinkable to find a Synopsys booth at SemiCon West. But this is now, and there they are, evangelizing for closer cooperation between design, manufacturing, and test engineers. It's a message with the ring of truth and the sheen of long and frequent repetition to it. But like calling for peace in Somalia, calling for inter-technology cooperation in the IC world isn't always the most rewarding of pastimes.

Synopsys appears to have stopped waiting for evangelism to work, and to have started building point solutions and gradually bringing them together to exchange data. The hope, according to Synopsys group director for manufacturing products Tracy Weed, is to fuse the data coming from existing point tools with new fault-detection and classification products into a single expert system. "We want to be predictive, not diagnostic," Weed explained. "We want everyone to know the yield sensitivities before tape-out, rather than only spending the time diagnosing yield problems afterwards."

A step in that direction is simply to capture the data that is already low-hanging fruit in various stages of the process. But this is not necessarily politically easy. It makes sense, for instance, as long as you have a wafer on the test head, to collect diagnostic information on a failed die rather than just detecting a failure and moving on. But that increases time on the test head, which increases direct costs, which decreases the test manager's compensation package. So even though tools now exist that could fuse such diagnostic data with the physical and logical design databases to point to a specific problem, the data may never be collected in the first place.

The situation may be somewhat more advanced in design and manufacturing. Designer flows document the physical locations in which DRC, critical-area analysis, litho or CMP simulation, and similar tools have worries. That data is available, but not in a format compatible with manufacturing data. Process engineers, similarly, have enormous databases of tool logs, inspection data, and APC data. But that data isn't readily accessible to designers, or easily matched to physical features or to netlists.

In too many organizations design, manufacturing, and test each have their specific charter, and none of those charters includes direct responsibility for yield learning on a specific design. They must work together, but they are incentivized not to. "Even in some pretty large companies, the primary yield analysis tool is still Excel," lamented Sagan Kekare, senior product marketing manager on the Synopsys project.

But slowly, primarily within the IDMs where you can get managers for all three disciplines into one conference room—and then lock the door—cooperation is building. It's still a long-term project, even though increasingly the point-of-contact tools to collect the data are in place.

Related entries in: Semiconductors | Yield Management |