Practical Chip Design

When major announcements at DAC are in short supply, the challenge becomes one of teasing trends out of the random background of releases, panel statements and off-handed comments that one hears around the show. It is perhaps an unreliable pursuit, but a diverting one. So here is an offering: both the meaning and the significance of low-power design are beginning to change for SoC designers as the first big design teams start taping-out 65 nm designs.

The meaning of the term is changing as the circuit-level emphasis shifts from relatively passive techniques to highly invasive ones. This is not to discount system-level energy-saving techniques: these are still the most powerful in their effect on total energy consumption, and yet the most poorly understood and least supported by the tool industry. Measures such as metrics for the inherent energy efficiency of algorithms, tools for managing memory hierarchy to minimize energy loss from load/store/fetch activity, and decisions to implement algorithms in sequencer-controlled pipelines rather than stored-instruction processors are all extremely powerful energy-management moves, but they tend to be neglected by chip designers. There is another whole subject here about the difficulty chip architects and implementers have in talking to, let alone reasoning with, software developers. It’s a human rather than technical issue, but it probably accounts for the vast majority of the electrical energy wasted in today’s systems.

But to return to our subject—for most design teams today, low-power design means choosing a low-power process, reducing the operating voltage somewhat, and applying relatively simply but effective techniques for clock gating and suppression of spurious logic state transitions. These are relatively well-understood techniques, and fit within conventional tool flows. But the kind of design techniques tool vendors are talking about this year go to a quite different level, altering the structure, function, and verifiability of the resulting circuits in their quest to cut both static and dynamic power.

These techniques include using voltage islands, each island operating at the lowest voltage consistent with its performance needs. This technique is now being pushed further to dynamic voltage control, so that the voltage on a block can be controlled based on its performance needs over the predictable near future. (Of course the phrase “predictable future” implies some ability to predict the behavior of the software. See above.) In addition, advanced designers are using power gating: actually shutting off the supply voltage to blocks that are not currently active.

These are invasive techniques. Voltage islands must be isolated from each other by isolation cells and level shifters. Dynamic voltage islands obviously create even more complex needs in this area. The impact on timing analysis, when a block may have four or five different timing files, depending on what voltage it is using in a given state, is to enormously increase the number of corners for timing verification, signal-integrity analysis and, yes, power closure. Further, the development of clock trees and especially test and diagnostic circuitry is complicated, as these circuits must track the supply voltage changes in each block and not accidentally introduce sneak paths between voltage domains.

Power gating is potentially even worse. The sequence with which a block is powered on and off must be carefully planned and managed to avoid physically destroying components or creating unwanted states. Wanted state must be somehow saved, in shadow registers or in a memory somewhere, and reliably restored. This means that turning the block off and on requires significant circuit overhead beyond the simple addition of power switches, and it introduces timing delays. This in turn means that if the power gating isn’t planned with a precise knowledge of the behavior of the application software (see, once again, above) it can end up increasing, rather than reducing, energy consumption.

Power gating for analog structures and memories is still, for most design teams, too ugly to contemplate. So analog circuits tend to run at fixed supply voltages, and memories on, at best, slightly variable voltages based on required access times. All of this often requires instantiation of local point-of-use voltage regulators, which further complicates layout and adds even more not-terribly-efficient analog circuitry to the design.

Tools are finally being used to help designers with some of these issues, but to date the tools are new and cover far from all the decisions a design team must make. Vendors are of course claiming success, but the jury is still out on actual user experience—I hear conflicting stories. In some areas, such as planning for state save-and-restore for power gating, there is little or no tool support today. The process becomes just another mode that must be designed into the RTL, synthesized, verified and tested. For issues like DfT with dynamic voltage islands, there may still be outright incompatibilities.

This makes the change in the significance of low-power designa crucially important shift. At even 90 nm, low-power design was something you did in response to a specific application requirement, such as the need to operate for longer than seven minutes on a single battery charge. At 65 nm, according to tool vendors at least, low-power design is something you do so that the chip can work at all. It is no longer a response to the application, but a response to the inherent logic density and leakage current of the process. Do a conventional design, and you will end up either with a very sparsely-populated chip, a very slow one, or with liquid cooling.

This suggests that tools for invasive low-power design will be a gating factor in the industry’s migration to 65 nm and certainly beyond. If these tools follow their usual three-year life-cycle arc from unreliable to correct but hopelessly complex to mature and useful, there will be a serious impact on foundries’ ability to sell 65 nm wafers. And if there’s one thing that increases the--shall we say—intimacy of the relationship between the foundries and the EDA industry, it’s an obstacle to wafer shipments. This could get interesting.