Practical Chip Design

May 19 2008 12:00AM | Permalink | Email this | Comments (3) |
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One of the known facts about power reduction in SoC design is that the earlier in the design flow you can make reductions, the more effective they are likely to be. Architectural changes can make integer-factor differences in power, where major reworks during physical design may only save a few per cent. Another truism is that there is no substitute for experience. Some architects and RTL designers seem to have a built-in block-level power analyzer in their brains, and to instinctively implement things in very energy-efficient ways.

Sequence Design, already a leader in post-synthesis power analysis tools, has pondered these points, and come up with a tool suite—PowerArtist—that attempts to automate some of those best practices that expert designers use during RTL design. The format is a fast, interactive filter that scans the RTL design, makes some changes automatically and recommends others.

Rather that relying on some abstract metaphysics, PowerArtist uses some very simple heuristics, such as "it's a bad idea to not use enable pins if you want to do clock gating" or "signal activity on a disabled input is dumb." Everybody knows this stuff, but systematically applying even such simple observations across an entire SoC calls for more managerial control and individual discipline than most design teams can muster. Even Japanese design teams, fabled for their discipline, report that they find power reduction a major challenge, according to research conducted by Sequence.

It gets a little intricate describing all the bits and pieces in PowerArtist, just because it is a collection of heuristics assembled under a graphic user interface, rather than one grand algorithm. But here's a quick tour.

According to Sequence's survey data, the three areas in a typical SoC in which the most power is consumed are, in order of descending importance, clock trees (30 to 60 per cent of system power), memory instances (20 to 50 per cent), and datapaths (a surprisingly distant third place.) Accordingly, PowerArtist has a set of things to do for each of these types of structures.

In the clock tree area, PowerArtist concerns itself with register enable signals and clock gates, with four explicit algorithms. The first two tools simply ensure that as many registers as feasible are gated by either suggesting appropriate enables for them from earlier in the logic cone, or by automatically creating new enables. The third tool works with the user to identify periods of time when a clock is enabled but there can be no activity on the inputs of the register. And the fourth tool identifies registers on which, based on activity analysis, clock-gating circuitry will or will not save power overall. The idea here is that if the clock will only be disabled for a relatively small percentage of the time, the enable net will probably use more power than gating will save. This information the tool passes on to the synthesis stage via constraints.

Similarly, there are three tools to deal with memory structures. The first simply automatically gates-off memory clocks when the memory is proveably inactive. The second tool interactively splits up wide memories into smaller structures to save power. And the third tool, again interactively, identifies activity on the memory's write pins when the memory is not in write mode, so that the user can gate off the source of the activity.

The set of tools for data paths is quite similar. Three tools look for data activity on unselected mux inputs; and for unnecessary activity between datapath stages, both on clock edges and during clock cycles. Again, the unnecessary activity gets flagged so the user can hunt down its source and disable it.

All of these tools scan the RTL, in some cases in conjunction with a test vector file that indicates expected activity levels. As mentioned, some of the tools automatically make surgical edits to the RTL, without disturbing its structure. Others report back through the user interface and suggest modifications to the RTL. There is also provision under the user cockpit to use a LINT-like power screening tool, and to add in user-defined checks.

There are some preparations necessary to make the tool effective, according to Sequence senior technical marketing manager PT Gupta. Obviously, you want to have done everything you can at the architectural level to make the design energy-efficient. Also, you want to have already done whatever work you intend to do on creating voltage islands, instituting dynamic voltage-frequency scaling, power gating, and sorting out the use of cells with different threshold voltages.

It is also vital, Gupta emphasized, to understand your chip's duty cycles and activity levels going into this process. If you don't really know how the chip will behave in use, you have little hope of optimizing its energy consumption, even with the best of tools.

The cynic could argue that at this point any competent RTL team could do the same things that PowerArtist does, by simply using their experience to sort through the design and spot the errors. But in practice, design size makes this infeasible, schedules make it unlikely, and reality makes in uneconomical. The tool is offering to do what you wished you'd had time—and the focus—to do for yourself.

There's quantitative evidence behind this offer. Sequence claims that PowerArtist has saved anywhere from 13 to 69 per cent of power in actual customer chip designs. And these are real chips, done by real, skilled design teams. They aren't marketing case studies.

Those figures, if not a full justification for running out and getting a $220,000/year license for the tool (which by the way is available at the end of June) are certainly justification enough for any design team to review their RTL coding practices with a hard look at energy-efficient design, and maybe send everyone through another round of design-for-energy boot camp.

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