Practical Chip Design

Altera announced this morning that they are now shipping one member of the Stratix IV GX FPGA family. For the record, this is the first device to ship on TSMC's 40 nm g process, and probably the first FPGAs to enter production at the 45/40 nm node. The devices have been described at some length previously, when they were announced last spring. But the fact that the first member of the generation to ship is a GX part—with a complement of on-chip high-speed serial transceivers, SerDes, and hard-macro PCI Express gen-2 controller blocks—brings up a very interesting point about the growing importance of high-speed serial interconnect to IC designs.

The decision to ship the GX first could not have been an easy one for Altera, and had to be based on customer demand, not on convenience. If you look at a die plot, the transceivers and PCI Express logic take up nearly a fifth of the die area—nearly as much real estate as the entire general-purpose I/O ring. The technology is bracingly difficult to develop and verify, the power consumption is non-trivial—although the blocks can of course be shut down—and the impact on yield has to be significant. But according to senior director of product marketing Dave Greenfield, the chance to support 8-lane PCI Express gen-2 and DDR-3 and to exploit the 40 nm process to improve jitter specs at the same time was too good to pass up.

Greenfield said that Altera relied heavily on design reuse to minimize the risk of leading with the GX parts. But defining just what you mean by reuse becomes difficult in this context. "There are different levels of reuse," explains Altera vice president of IC design Richard Cliff. "You can reuse anything from functional specs to circuit designs to layouts to polygons. But what makes sense depends on the situation."

In Altera's case, for example, the DDR-3 controller logic was pretty much reused intact from Stratix III, apparently at the netlist level. It was up and working in the first three days of silicon effort, according to Greenfield. But it proved much less easy to port the analog blocks required for the high-speed transceivers.

Cliff's team took a very interesting approach to the porting problem. One of the first test-chip designs the company sent off to TSMC was a complete Stratix III design, intact except for a few adjustments to the layout. The team knew this would not work, but they expected to learn important information by finding out exactly where it failed. And that they did. TSMC ran months of wafers using this mask set, doing process development while Altera did model development and methodology development, all in parallel. "We learned a great deal about sub-micron effects from that exercise," Cliff says.

The learning showed up as adjustments to the layout of reused blocks. Many issues descended on the layout at 40 nm, including a plethora of layout dependencies that impact transistor performance by altering the strain engineering on individual transistors, a whole new host of lithography-related restrictions, and even the fact that at 40 nm, transistor performance depends on the orientation of the transistor relative to the silicon lattice structure. "In one case, we found out that a layout technique that was preferred at 65 nm was actually bad at 40 nm, and we had to adjust our layout," Cliff said. And then of course there is the whole matter of process variations, which just keep getting worse and more local.

So there was a significant effort in getting the GX transceivers ported, and another significant effort in verifying and characterizing them. Plus there was the concern that even when the new layouts met all the process requirements, the circuits might not meet performance specifications across the process and operating windows. This was particularly important for jitter, Greenfield said, since the chips had to meet the stringent requirements for PCI Express gen-2. The result Altera is quoting, of random jitter of 1.27 ps at 8.5 Gbits/s, compared to 1.8 in the 65 nm generation, appears to settle the question.

Altera is not the only vendor to see growing importance for high-speed serial support. Fledgling FPGA vendor Achronix was at an FPGA conference in San Jose last week showing samples of their first high-speed devices on a test bench doing high-speed serial, and bragging about their eye diagrams. Clearly the main differentiation of the chips is their ability to micro-pipeline logic to achieve extremely high clock frequencies. But strategic marketing manager Denny Scharf said that a significant amount of interest in the new devices is due to their SerDes performance at 10 Gbits/s, in such areas as Infiniband-based processor clusters and passive optical networks. The ability to integrate 10 Gbit PHY blocks with MACs and functional logic without resorting to multi-die packages is a big deal.

But it is far from a done deal, argues Bharat Tailor, director of marketing at Gennum. The company recently announced quad 10 Gbit clock-data recovery chips (CDRs,) indicating pretty clearly that they don't think integrated PHYs are the whole answer at this frequency. Tailor says that the need for discrete CDRs is a matter of application. "Long signal distances or densely-packed boards can take jitter and attenuation problems beyond the reach of the SerDes and transceivers you find on ASIC devices," he said. "There are physical limits to equalization on an ASIC, for instance, that pretty much keep you from doing more than 20 dB equalization at 10 Gbits/s. There are limits to the input sensitivity of the receivers you get on ASICs, and their tolerance for jitter may not be great." All of these issues call for external CDRs to perform transmit de-emphasis, receiver equalization, and management of the system-level jitter budget.