Practical Chip Design

Leveraging high-level synthesis technology developed at Synplicity, Synopsys this week introduced a unique approach for generating synthesizable datapath RTL from algorithm descriptions in the Matlab environment. Unlike other high-level synthesis tools, which start with a system description in SystemC or another C dialect, Synopsys's Synphony tool starts with the native scripting language of Mathworks Matlab, M-files. Synopsys refers to this mathematics-like scripting as the M Language, which is not to be confused with the M (or MUMPS) language used to develop database applications.

Synphony offers a two-step conversion process. After algorithm designers have explored and verified their algorithm in Matlab's implicitly real-number space, Synphony converts the model to fixed-point using a tool called M-Compiler. This automatic conversion step bypasses what would ordinarily be months of manual recoding from M-files into a model with fixed-width datapaths. At this point users may reverify the model in the Mathworks Simulink environment. In the second conversion step, Synphony then converts this fixed-point model into synthesizable RTL, in the process generating other useful files.

More specifically, in the first stage Synphony uses a Synopsys-provided IP library of fixed-point functions to generate a fixed-point model from the M-files, subject to constraints provided by the user. In this step the tool can either generate datapaths and propagate the path widths based on the requirements of the algorithm, or the user can explicitly intervene with the constraint file and set path widths directly. The tool reports encounters with the constraints, insertion of quantizers, and other important events. The model executes in the Simulink fixed-point management environment, allowing the user to relatively quickly verify operation, and to run the model against the original Matlab testbench to examine the effects of quantization.

Once the user is satisfied with the model, on to step two. The user feeds the fixed-point model and further constraints into the Synthesis Engine. This tool offers a number of optimizations, including pipeline insertion, resource sharing, and loop unrolling. It can also infer some interface structures—for example, inserting a buffer to pack a serial operand stream into a matrix. The tool also introduces target-specific optimizations for either FPGA or ASIC target hardware. The constraints files direct the optimizer to meet timing while minimizing area.

Along the way, the Synthesis Engine provides early timing estimates using its own timing engine, and it can call Design Compiler to get more accurate estimates on specific paths. There is at present no provision for power estimation.

As outputs, the Synthesis Engine produces an RTL file for either the Synplify or DC synthesis tools, a synthesis constraints file, an RTL testbench, and an ANSI C file that is a cycle-accurate representation of the RTL. The tool also extracts memory instances for passing to third-party memory compilers. The C output is intended for system-level verification, but, curiously, it requires wrappers to bring the code into a standard SystemC/TLM verification environment.