Practical Chip Design

The morning session at the annual Globalpress electronics forum this morning turned into a perhaps-unintentional arena for the ancient argument of whether FPGAs are replacing ASICs. The discussion began with Altera president, chairman and CEO John Daane restating the FPGA industry's long-standing claim that we have at last reached the tipping point where the displacement of ASICs and ASSPs by FPGAs will be a manifest fact. But the next two presentations in the program, by Tensilica CTO Chris Rowen and QuickLogic VP of marketing Brian Faith, quickly raised questions about Daane's confidence.

Daane rested his projection on several arguments. First, he offered a singularly sober economic scenario: that the end of consumers' ability to tap their home equity to support their lifestyles in the US and UK would bring an end—indefinitely—to rapid growth in the consumer electronics and personal computer businesses. That in turn would hit the entire semiconductor industry, but with those companies most exposed to the consumer and PC markets suffering worst. So Daane projected what he called a fundamental reset: growth of 1-3 percent for the semiconductor industry overall, but substantial contraction in the ASIC and ASSP businesses, which depend heavily on consumer electronics and PC sales. In contrast, he said that the FPGA business, which draws nearly half of its revenue from communications and over a third from industrial and military applications, would be much less harmed. He suggested that Altera, in particular, could see 5-9 percent growth in the near future.

This disparity, Daane said, would come in part from differences in end-market growth, but also from FPGA displacement of ASICs and ASSPs. He then offered the usual arguments for why FPGAs should be displacing ASICs and ASSPs: reprogrammability, lower non-recurring expense, and growing parity in die size. Daane backed up his assertion by saying that Altera's sales to its communications customers had been growing faster then those customers had, in his view proving that Altera FPGAs must be displacing ASICs in those accounts.

These points the CEO arrived at through an interesting stratagem. Daane claimed that last year almost 90 percent of ASIC design starts were at nodes of 130 nm or above, while this year Altera has begun sampling 40 nm FPGAs. He used this to justify comparing the die size, performance, and power of a 40 nm FPGA against those of a 130 nm ASIC, and claimed that on this basis, FPGAs would be an alternative for 88 percent of ASIC design starts.

As usual, in comparing programmability and NRE levels for FPGAs and ASICs, Daane did not discuss the growing programmability of ASICs and ASSPs, the increasing use of programmable accelerators, or the fact that the vast majority of ASIC and ASSP design costs are incurred for tasks—such as architectural and RTL design, verification, and software development—that must also be done, at essentially the same cost, for an FPGA. Nor did Daane address the considerable design reuse of hardware and software that mitigate the up-front costs of all chip designs these days. Nor did the CEO treat the question of whether declining ASPs in the communications and networking industry might have been the actual reason Altera's shipments to those companies grew faster than the companies' revenues.

In the question period following the keynote, the fine print continued to take away. Daane admitted that the actual revenue share of FPGAs compared to ASICs had remained quite small and relatively constant, stubbornly ignoring previous claims of a final tipping point. He said that customers' problems in getting some design wins into mass production and the decision of some customers to move to standard-product solutions instead of FPGA-based designs had led to this shortfall.

Daane also said, in answer to a different question, that in the automotive industry Altera is only focusing on applications within the cab, not contesting against ASICs for applications in the drive train, for example. Further, he clarified that FPGAs are still not competitive for really high-volume applications such as successful consumer products, so there is not likely to be much displacement there, either. After clarification, it appears that any displacement of ASICs and ASSPs will have to occur in some specific market segments.

Rowen, in his presentation, pursued the point of growing programmability in ASICs. Agreeing with Daane about the importance of programmability in principle, Rowen went on to illustrate how Tensilica CPU cores configured to specific tasks are displacing hard-wired logic not only in control applications, but in many data-plane tasks. In this way the cores can offer much of the power savings and compactness of dedicated hardware while still giving C-level programmability, Rowen claimed.

The CTO offered a case study with a recent product from Tensilica, the HiFi 2 audio processing core. In a departure from the company's early strategy of preaching massive computing power from large arrays of configurable processors, Rowen emphasized that a single HiFi 2 core could handle all the audio processing tasks for a Blu Ray player, for example. Or, he claimed, the core could handle all of the major digital audio broadcast standards, including both terrestrial and satellite, with only software changes. This would permit one ASIC or ASSP to serve an entire cost segment of the digital audio receiver market without the need for even a small FPGA companion chip.

Speaking of companion chips, QuickLogic's Faith came next, discussing the company's Customer-Specific Standard Product (CSSP) concept. CSSPs, Faith explained, include a combination of diffused functional blocks and programmable logic fabric on one die, combined with driver software and system-level verification benches for specific application areas. The concept gives users a very fast time-to-market, low-investment entrée into specific broad applications areas, Faith said, without sacrificing customer-specific features.

He illustrated his point with a new-product announcement, the VX-4. The CSSP is specifically intended to attach to the MDDI interface on a Qualcomm smart-phone SoC, interposing itself between the Qualcomm chip and the display. In this role the VX-4 would provide an in-line visual enhancement processor, frame-buffer capability, and customer-specified other display processing, as well as a customer-specified standard or custom display interface.

Faith said that like the VX-4, all CSSPs were targeted for high-volume areas that were not typical FPGA applications. But the chips are intended to serve as companions to a system ASIC or ASSP, not to displace it. Faith identified a spectrum of products, ranging from high-end smartphones to mobile Internet devices to netbook compact computers, as the intended markets. Explaining that the presence of application-specific hard-wired functions was essential to the value proposition, Faith said "You can't get designed into these devices with a fully-programmable platform."