Practical Chip Design

Two of the announcements coming out of CDNLive in Munich this week illustrate the degree to which tighter cooperation between EDA vendors is beginning to change the landscape. Cadence has reached out to two tool outside vendors—one for FPGA integration and one for system virtual prototyping—to extend the reach of two of Cadence's own existing tools.

In the first case, Cadence announced yesterday evening that it has worked with Taray to integrate that company's FPGA pin-assignment planning tool with key portions of the OrCAD and Allegro product lines. The Taray tool attempts to optimize pin assignments on FPGAs subject to the chip vendor's design rules and guidelines and a board-level floorplan. Since the tool understands constructs like standard interfaces and busses, it can group the pins for these structures appropriately. Significantly, the Taray tool works with multi-FPGA designs, so it provides a very useful way to get multi-FPGA-based ASIC emulation boards laid out.

The hope is that by integrating Taray's capabilities into Cadence's PCB tools, the resulting design flow will eliminate the gap between the provisional pin assignments the FPGA design team uses and the needs of the board layout and routing tools. Too often, according to Cadence director of marketing Hemant Shah, the FPGA design team makes pin assignments that seem reasonable from their point of view—knowing the internal floorplan of the FPGA design, but with little or no knowledge of the board layout. By the time the board designers get a package definition from the FPGA team, many decisions that will influence routing congestion, signal integrity, and the required number of layers have already been made.

This can force a delicate negotiation between the board team—which must face the possibility of much more expensive circuit boards and several extended design spins—and the FPGA team, which can see their entire mapping and timing closure go up in smoke if they have to move pins. By using the Taray and OrCAD or Allegro tools together, the board team can provide a board floorplan and a proposed pin assignment to the FPGA team early, before the filling up of the FPGA has started to make changes costly.

The same notion of alliance gets applied in an entirely different area this morning, when Cadence announces a tight integration relationship between Incisive Software Extensions and Virtutech's Simics system virtual prototyping tool. The benefit here is to extend Cadence's coverage-metric-driven verification methodology from just the hardware to a model of the hardware combined with all the system and application software.

In principle, Simics will provide the device under test: a system-level simulation that includes all layers of the end-product software running on a model of the end-product hardware. Using Simics, you can perform pretty much all the debug operations you would do with a normal software debug environment, but with the software executing on a fully-functional simulation model of the hardware. This includes, tracing, breakpointing, and executing backwards, as well as examination of the hardware state.