Practical Chip Design

In recent processes—both 40 nm digital processes and the latest larger-geometry power processes—designers are learning to be skeptical of traditional extraction tools. At 40 nm, structures are often very close together and quite geometrically complex. Cross sections are not always even approximately rectangular. Current densities are far from uniform. And it's not possible to ignore the presence of barrier and seed layers around the bottom and sides of metal lines.

Process-modeling engineers are out in front of the problem. Extraction experts say that there is enough information in most advanced-process PDKs to deal with all these issues. The problem is that conventional 2D and 2.5D extraction tools don't use that data effectively. So physical-design teams may use a conventional extraction tool on a chip, and then go back and apply a field-solver—accurate, powerful, and an order of magnitude slower than extraction tools--to specific structures that they expect to be problematic.

That's great if the structures in question are easy to identify and are used over and over unchanged—things like CCD cells in an imaging chip or three-dimensional transistors in an advanced DRAM process. But what if there are hard-to-model structures occurring throughout the interconnect as well? Or what if there are several different very large power devices in the design? Are physical designers supposed to comb through the entire layout looking for trouble?

As you probably guessed, Silicon Frontline has a potential solution: a full 3D extraction approach that the company claims has the accuracy of field solvers, but runs at nearly the speed of 2D extraction tools. The company is offering its technology in two separate tools: a general-purpose extraction tool called F3D, and a tool specifically for extracting effective resistor values and current densities in situations with highly nonuniform current distribution—primarily in power devices—called R3D.

The basis of the new tools lies in breakthrough algorithms for both meshing and solving, and in a geometry database that permits Monte Carlo analyses in reasonable run times, according to CEO Yuri Feinberg. Naturally the company is not discussing the algorithms, but it appears that the developers have found a way to apply their knowledge of silicon and metal structures to produce sparse matrices susceptible to the latest advances in sparse-matrix solvers. "The meshing algorithm is very intelligent," Feinberg offered. The result, according to Feinberg, is a very fast solver that allows the use of 3D analysis on full chips, not just special structures. And this at accuracies typically within a few percent of silicon.

The tools can take in either the output of an LVS system or pure GDS-II combined with a rule deck in a standard language. They produce synthesizable netlists. While Silicon Frontline is still early in the field deployment of the two tools, Feinberg says that adapting them to a new challenge is not a matter of reworking the algorithms, but of resetting the knobs. "Recently we did an analysis on a very interesting capacitively-coupled analog circuit," he said. "We just tuned up the convergence criteria a bit and the tool worked."

Silicon Frontline cites impressive results. For an example they offer the process characterization on a 40 nm process. The hard bits included issues with the patterning of via arrays and use of aggressive metal fill, the latter having significant impact on parasitic capacitance throughout the interconnect. Down at the surface, the process included multi-fingered devices. It became apparent that gate-to-channel capacitance was going to be a big issue in the device models. And just to keep things interesting, device-to-device interactions turned out to be significant as well.

The process team applied conventional extraction tools on test chips, and managed agreement with silicon within about 30 percent. But using F3D, they achieved agreement within 2 percent. And this with runtimes similar to those of the conventional tools.

Another major success story has been modeling raised source/drain finFET transistors and via arrays for a major foundry. "There was simply no way to get to a realistic estimate of the model parameters for these finFET transistors with 2.5D tools," Feinberg said. We were able to extract them successfully.

Feinberg emphasized that while the most headline-grabbing results might be coming from advanced processes with F3D, the contribution of R3D to the power semiconductor industry will be equally important. The company claims that the resistance-extraction tool can take on the worst problems in modern power devices, including large layouts with lots of small features, via arrays, and irregular 3D structures, achieving first-time convergence without pre-fitting. Results include not only accurate extracted resistance values, but an understanding of current densities, allowing better design of power-device gate structures and early warning on electromigration problems, for instance. The company claims that R3D can trim literally months off a physical verification cycle.