Practical Chip Design

The lead-off session at the undeservedly little-attended Hot Interconnects conference at Stanford this morning examined the growing challenge on chip interconnect technology as today's small-scale multicore processors evolve into chips with tens or hundreds of processor cores. Papers examined two primary issues: the increased need for on-chip bandwidth between processors and memory instances, and the need for bandwidth between the chip and external DRAM, the latter on the assumption that memory hierarchies may come and go, but DRAM will be with us forever.

The papers all emphasized the same overriding issue: power. For projections say that we will run out of power to drive the interconnect, and capacity to cool it, before we run out of physical area for laying out more wires. Interestingly enough, three papers came to the same conclusion: it is time for architects and process engineers to begin thinking seriously about photonic alternatives to traditional resistive-capacitive metal interconnect.

The first paper, presented by Michael Tan as part of a team at Hewlett Packard, discussed a novel way to fabricate a tiny optical waveguide with embedded pellicle taps to form an optical multi-drop bus between an IC and a set of DIMMs. Such a waveguide, the groups research shows, could support up to 8 taps over a length of 30 cm @ 10 Gbits/s when driven by a 1 mW VCSEL.

The waveguide technology, according to Tan, dates back to the days before the use of optical fibers, when researchers at Bell Labs proposed tiny hollow metal channels to carry light over long distances. The HP team fabricated theirs by sawing triangular grooves in the surface of a silicon plate with a dicing saw. The team coated the inside surface of the slot with silver and covered it with a gold-coated aluminum cap plate. This formed a square-cross-section waveguide with an approximate width and height of 150 micrometers. As Bell Labs had expected, illuminating the waveguide with a very carefully aligned VCSEL produced numerous low-loss transmission modes.

The team fabricated the taps by cutting gaps in the waveguide and inserting pellicle mirrors. As it turns out, light in the waveguide is sufficiently collimated that a small gap does not create serious attenuation. By adjusting the degree of reflectivity and transmission of the mirrors, the team was able to even out the optical power delivered to each tap along the waveguide. A similar approach allows a return waveguide to collect optical data from the taps and aggregate them at the originating end of the waveguide. Hence the structure can form an optical equivalent of a FBDIMM bus structure, but with the potential for less power, less signal integrity issues, and very high data rates. Laser and optical connector costs remain an issue of course.

The second optical paper, from a joint project at MIT and UC Berkeley, looked at on-chip use of photonics, describing an optical waveguide, ring modulators, and optical-to-electrical translators all fabricated in a nearly-standard CMOS process.

The key to implementation on-chip is a polysilicon waveguide undercut by an air gap to reduce leakage into the substrate. Ring modulators as small as 3 micrometers radius allow wavelength-division multiplexing on the waveguide. By using the SiGe material already present in CMOS processes as a strain-inducing medium, the team was able to fabricate photodetectors operating in the 1200 nm region. Optical power comes from an off-chip laser source.

The researchers proposed combining these components to form a dense mesh network that would interconnect processing cores, on-chip memories, and, through suitable optical couplers, off-chip DRAM. The team projected that such an arrangement, used in a 256-core SoC with 16 external DRAM modules, could produce 8 to 10 times the aggregate bandwidth of an electrical interconnect system at the same power level.

A third paper, from the CS and EE departments at Columbia University, explored non-blocking network-on-chip structures for use in single-chip multiprocessors. Using silicon waveguides, ring modulators, micro-ring routing switches, and SiGe detectors, the team employed similar component technology to the MIT/Berkeley work, but in quite different topologies. The results, as demonstrated by simulation of a large-FFT computational unit, were similarly impressive.