Practical Chip Design

The private debate continues among process engineers as to what will be the gate stack of the future. Intel seems to have already committed to a high-k, metal-gate path. TSMC has been publicly resolute in sticking with silicon oxy-nitride dielectrics and poly gate electrodes. Other vendors are investigating many options. But about the only public visibility of this private debate comes from the occasional paper to surface at a technical conference.

This week is bringing quite a bounty of such papers, from the VLSI Technology and Circuits Symposium in Kyoto. Two gleanings from the bounty suggest two remarkably different data points—although at two very different process nodes—for the search for the golden gate stack.

In one paper, presented Monday, Toshiba researchers described pulling out all the stops, materials-science wise, to produce a useful planar metal-insulator-semiconductor FET for use at 16 nm and beyond. The device differs in almost every possible choice of material from today's silicon-channel MOSFET with its oxide dielectric and poly gate.

The Toshiba device employs a germanium channel to get the necessary drive current in such a tiny device. This should be a source of enormous amusement to readers old enough to have suffered through Ge power transistors in the first generation of solid-state audio amplifiers. But the fact is, Ge offers the kind of very high hole mobility you need at these dimensions.

The problem is that Ge channels don't work well with currently-envisioned high-k/metal-gate gate stacks. It has been shown that you can improve the interface by embedding GeO₂ in the dielectric layer, but the material has a relatively low k, and makes for an ineffective dielectric material. Toshiba researchers responded to this challenge by finding a reliable way to fabricate an atoms-thick layer of a strontium-germanium compound between the channel and a conventional lanthanum-aluminate high-k dielectric film. The Sr-Ge compound acts as an interface between the Ge channel and the conventional high-k stack. The result is a transistor with over twice the overall mobility of a comparable silicon transistor. The researchers also reported that the gate structure should be scalable beyond the 16 nm node.

Working on a more immediate problem, researchers at TSMC reported today that the company has achieved "good" yield on a 64 Mbit SRAM structure in 28 nm low-power CMOS. This is of course a qualification step on the way to introducing a commercial 28 nm process node.

The company said that this new process continues to use the conventional silicon-oxy-nitride/poly gate stack to which TSMC is so loyal. Combining aggressive oxide scaling, even more aggressive strain engineering, and who knows what else, the company has managed to squeeze at least a 25 percent improvement in speed—or alternatively a 30 percent reduction in active power—from the transistors, compared to their own 45 nm process. In the press release there was no discussion of leakage current or operating voltages, other than to say that the SRAM cell exhibited a good V_{cc_min}.

Of course lumbering along behind the demonstration SRAM is the full kit of a commercial process, including interconnect technology, RF and analog models, multi-oxide-thickness options, and so forth. TSMC says it is still on track to release the 28 nm node early next year.