Practical Chip Design

In recent conversation Xilinx president and CEO Moshe Gavrielov sketched the broad outlines of a future for the FPGA industry that looks far more application-directed and design-tool-oriented than even the recent past. You can almost detect between the lines that, as in the advanced microprocessor world, scaling is slowing down for FPGAs, and other issues are becoming more important than just getting to the next process node quickly.

These changes are based on Gavrielov's strategic view of Xilinx: that it should remain a growth company, not become a mature cash generator. And that means, the new CEO said, "we have to have a business model that is scalable. If we continued to grow as we are today, technical support would balloon." That, Gavrielov projects, would lead to support costs gradually eating away the benefit of growing sales.

Instead, Gavrielov wants to see a major realignment in the way Xilinx addresses its markets. First, "We need to streamline the way we serve the horizontal markets," he said. This means making the design tool flow so simple—in part by basing it in rich intellectual property (IP) libraries—that the typical design requires little or no tech support to get through timing and power closure and into production.

This goal will require two technology achievements. The first will be continued pursuit of the technology curve. A simple design flow necessarily extracts some cost in power, area, and performance. So an "FPGAs made easy" design flow can only serve applications for which semiconductor technology has rendered the underlying silicon more than fast enough, more than dense enough, acceptable in power, and affordable. That is already the case for some applications, but the Xilinx chip design teams must keep driving area, power, and delay down to expand the solution space for this simple solution approach.

The second achievement will have to be a really simple design flow—something that doesn't start out looking like clicking Lego blocks together, but end up dumping the user into a closure procedure borrowed from the physical design world. Such a flow has to be simple, and must express the design in relatively abstract terms all the way to sign-off. And it has to deal with physical issues--such as variations, timing, and power--in these simple terms.

Those two achievements would reduce the cost to Xilinx of servicing its horizontal market. Then the company could turn its best resources on what Gavrielov sees as the central problem: the increasingly application-specific use of FPGAs as the hearts of integrated systems, rather than as the glue around them. "We have to focus on a few vertical markets," he said. Questioned on this, Gavrielov says that he is not talking about architectures that look like ASSPs with added areas of programmable logic, but rather chips that look like FPGAs, but with increasing content of application-specific soft, or in some cases hard, cores.

Focus on vertical applications would permeate the silicon design, the tool flow, and the IP libraries, both internal and third-party. The result would be an application-specific design environment for each of a chosen few applications, complete with its own synthesis scripts, mapping tweaks, IP, and verification flow. "One of the biggest challenges has been getting IP into the verification flow," Gavrielov reflected. "Verisity made some huge steps forward, but nothing as dramatic has happened since then."

This applications focus also has its implications for Xilinx's hardware designers. It means, for one thing, that in some cases Xilinx will be developing and integrating application IP that has nothing to do with programmable logic fabric. An extreme example would be RF blocks. "I think probably 70 to 80 percent of the applications we see would not benefit from integration of analog or RF," Gavrielov estimated. "They are better off on separate dice. But there are some cases. High-speed serial I/O blocks, for example, are already mainstream in FPGAs. And in some wireless applications we might chose to address, integration of RF functions might be compelling."

Gavrielov's view of a scalable growth strategy, then, has major implications for both FPGA users and for Xilinx's internal engineering development. For most users, the result would be greater simplicity in exchange for some loss of control over the details of the design. For a specific few users, it would mean an entire design environment tuned to their needs and their vocabulary. In both cases, the actual details for the FPGA hardware would continue to recede toward invisibility.

For Xilinx, this future means that the company must substantially expand its tool development effort, and even move beyond tools into the application-specific software necessary to turn a powerful FPGA and an IP library into a full reference design. Further, this future requires Xilinx to remain expert at being one of the first users on each new process node and to be expert at producing an FPGA architecture there--but also to bring to the new node a growing library of complex application-specific IP. It's a tall order.