Practical Chip Design

It’s standard for the foundry industry these days to offer at least two or three versions of their process at each major node. There is usually a low-power version, a standard version, and in some cases a high-speed versions. Other modules, for RF, precision analog, embedded DRAM and the like, may be added later as options.

Lately the trend has been for the high-speed version to become much less standard. Design teams reaching for the edge of the performance envelope usually end up in a joint development that involves both some custom cell design and some back-end tools not applicable to the standard ASIC flow. So things like CPUs or high-end graphics chips aren’t exactly ASICs, at least in the way they are designed.

With its announcement this week of its plans for 45nm, IBM has stepped away from the normal pattern. There will be standard (SF version) and low-power versions of the 45nm ASIC process, as usual. They will be similar to what everyone else has been discussing, using immersion lithography on critical layers, using the next generation of low-k goop for inter-metal dielectrics, and avoiding high-k/metal gate stacks like the plague. They will not use the much-discussed air-bridge interconnect structures.

The difference is that the high-speed version of the IBM process will be offered only in SoI, not in the bulk CMOS technology used in the other two versions. This is the first time one version of an ASIC process has used an entirely different technology from the other versions. It is also the first time IBM has offered SoI to customers through a conventional ASIC flow, rather than a closely-coupled joint development.

The good news is that this will bring the benefits of SoI—a sweeter trade-off point for power, speed and area—to a wider audience. According to IBM, the notorious issues in SoI design, such as the floating-body effect, have been encapsulated in the cell library and models so that the ASIC designers does not have to deal with them at all, or even really be aware of them.

The trickier part is that this means the libraries and hard IP for the high-speed version will be entirely separate from the libraries and physical IP for the SF and low-power versions. There will be roughly the same functions in the cell library, so that synthesized structures should look the same at RTL. Of course the timing and power data will be different, as they would be for any high-speed process. But things like PLLs will may be quite different. Just how designers would go about implementing analog functional blocks in the SoI high-speed version is unclear. Also, whether such future modules as embedded DRAM will appear in all three variants of 45nm is a question.

The move shows a bit of daring on IBM’s part, both for technical reasons and for the marketing risk: the term SoI has so far been just about as intimidating to ASIC designers as that most frightening of goblins, asynchronous design. Whether design teams will accept that IBM has pulled the fangs from this notoriously difficult technology remains to be seen.