Practical Chip Design

For some reason system management hardware and system reliability seemed to keep coming up at ESC this year. In the past it has not been that common a topic outside a few specific communities, but the concern for high reliability, and in particular for what happens when a system does fail, seems to be growing. Today most of the discussion is at the board level, but inevitably this will move to the chip level for designers of SoCs.

Simtek—a non-volatile memory and IP company—has been involved in this discussion for years. The company's key technology is a ten-transistor SRAM cell that has a built-in non-volatile shadow memory. According to Simtek VP Marketing Gran Hulse, the cell combines a conventional 6-T SRAM cell, with access times as fast as 25 ns in 130 nm, with an integrated 4-T SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) non-volatile cell. SONOS, if you haven't been watching the angst over the future of Flash technology, is an alternative to floating-gate Flash. Roughly speaking, you program a SONOS transistor by trapping charge in the Nitride impurities embedded in the dielectric layer of an otherwise-normal, if rather thick, transistor gate region. The mechanism for this charge trapping appears to be Fowler-Nordheim tunneling, which is slow but very low in energy consumption per bit programmed.

In any case, Simtek developed this cell with the idea that many real-time systems needed to save the contents of their SRAM on impending system failure—usually, on a glitch in the power. Traditionally, systems have done this by having battery back-up on the SRAM, or having an entirely separate DC supply that held the system up just long enough for a memory save. But if the save means transferring the contents of SRAM to Flash or disk, that could be a lot of current over a long period of time. The Simtek solution still uses the idea of dumping SRAM into NVRAM while an emergency supply holds up the power rail. But because of the shadow-RAM architecture, this transfer happens in parallel, in about 13 ms, independent of the memory capacity. And it requires only the RAM array itself to be powered up, so the current can easily come from a small capacitor.

Hulse says that the company started out marketing SRAM chips into military applications. Then the RAID people became enamored of the technology, since they tend to have all their file-mapping tables in SRAM—a very inconvenient place for it in the event of a power glitch. But now, Simtek is starting to see interest in other areas of embedded computing: machine control, medical instruments—any application in which it would be problematic to lose the state of the system during a power glitch.

These new applications, in turn, are pressing the company to move to higher bit densities. Hence today the Simtek will announce their first 8 Mbit chip family, offering 25 ns and 45 ns speed grades. The timing of the devices for conventional read and write is just the same as an equivalent-grade SRAM, and the power is similar, according to Hulse.

The item that Simtek is not announcing, but that makes the company interesting in this context, is that the technology is also available under license as silicon IP. As IP, the memory requires a little more than just drop-in replacement of existing SRAM. The cells are larger, so layout will be different. Additional voltages are necessary for the dump-to-NV operation, and an external controller is necessary to control the back-up and restore processes. In addition, formation of the SONOS gate is not a standard part of CMOS logic processes (or Flash processes, for that matter) and it requires two additional mask layers.