Practical Chip Design

Mar 26 2008 2:44PM | Permalink | Email this | Comments (2) |
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In a presentation at ISQED last week, Mentor Graphics verification and test division GM & VP Robert Hum presented an interesting good-news/bad-news scenario. On the good-news side, Hum said that after years of verification costs gobbling a larger and larger fraction of the total engineering budget for chips, and in fact after years of verification cost rising faster than revenue per design, the rate of increase in verification cost is finally starting to moderate.

On the bad-news side, Hum presented a problem that could very well reverse that trend. The problem is yield. Hum pointed out that many designs today in consumer and communications markets have very short lifetimes—in fact, for any one mask revision, the product life is shorter than a full yield-learning curve for the mask set. I state it this way because at 90 nm and beyond, much of the yield loss is pattern-specific. That means that the yield learning curve begins when the foundry starts using a particular mask set, not when they start running a particular process variant. So every revision to the design starts the yield learning process over again, at least for layers that have changed and nearby layers that might be influenced by the changes.

If you don't build a given chip long enough to get through the conventional foundry yield learning curve, you have two choices: live with sub-optimal yield (experienced design managers may snort in derision here) or accelerate the curve. Obviously, other things being equal, we will choose option B.

So here's the catch. According to Hum, the best way to accelerate yield learning is detailed failure analysis. But early in the product life, when you need to be jumping on the failed dice to analyze them, there are far too many little dead ones to do an FA on each. So, Hum says, you have to perform not just pass/fail testing, but full diagnostics on each failed die—while they are sitting on that expensive test head—to identify and categorize the failure modes. They you send representative dice for each failure mode to the FA lab, they identify the failure mechanisms and feed the data back to design for remediation, either with mask changes or process tweaks.

So where's the bad news in this? First, it means that along with DfT, the design team will now be responsible for designing full diagnostic capability into the test process. That will mean not only a lot more test code, but more hardware provisions for observing and modifying the state of internal nodes on the design. And that will add to the verification load all over again, since these hardware provisions and the diagnostic modes must be verified. Second, this means that some of the money potentially saved by a faster yield ramp will be spend on longer—early on, much longer—test time. The hope is that if the product has sufficiently high early volume, the yield savings will pay for the extra design and verification work and the extra minutes on the test floor. Yet another gamble.

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