Practical Chip Design

It still seems a little strange to be discussing FPGAs as possible components for use in smart phones and mobile internet devices, given the cost and power constraints inherent in those designs. But an announcement today from QuickLogic illustrates that in fact FPGAs can make sense sometimes even in these applications.

The announcement in question concerns the Visual Enhancement Engine (VEE), an in-line pixel processor based on the Apical Imaging iridix core. The engine is a roughly 250Kgate core that performs a number of image optimizations, including dynamic-range compression, color correction, and ambient-light compensation to both improve the viewing experience on rich media data types and reduce the backlight energy required for a good image. As such, the core is of obvious value to designers of hand-held equipment that will display photo-type images. QuickLogic developed their core as an implementation of the technology, and has been offering it to handset developers.

One result of the interest from the handset community, according to Brian Faith, QuickLogic vice president of marketing, was a series of requests for a version of the VEE that would work with Qualcomm's proprietary EBI 2 display port. EBI 2, used on some Qualcomm SoCs, provides streams of RGB data in a command-based format that differs somewhat from standard RGB. Accordingly, QuickLogic, working with at least one of said prospects, developed an EBI 2 interface block that could receive the incoming command stream, parse out the RGB information and send it to the VEE block in the correct format, or simply act as a bypass path directly to an EBI-2-enabled display for information that would not benefit from the visual enhancement algorithms. This interface block requires about another 50 Kgates.

QuickLogic intends to offer the VEE function in hard logic on a future customer-specific standard product chip. But a number of clients, Faith says, were in enough of a hurry to get the technology into a product that they asked about having the engine and interface blocks in an off-the-shelf FPGA. So QuickLogic optimized both blocks for use in a standard PolarPro low-power part. "The EBI 2 interface does not require faster serial I/O than we provide on the PolarPro," Faith explains, "and at up to 24 bit/pixel, wide-VGA resolution, the pixel clock is slow enough that an PolarPro implementation of the VEE can do the processing."

But what about the other two nemeses of FPGAs, power consumption and cost? According to Faith, the VEE in the PolarPro, running at a 20 MHz pixel clock—about right for wide VGA—consumes about 24 mA. In bypass mode, where the EBI 2 interface is simply passing the commands along to the display, this drops to under 1 mA. If the display goes into standby, the application can sleep the entire FPGA, cutting the current to about 100 µA. And the parts hibernate at under 5 µA. So depending on the use model you have in mind, the FPGA implementation may not be that big an addition to a hand-held system's overall energy budget. Certainly 24 mA would be noticeable if you were to sit down with a feature-length movie and put a stopwatch on the battery life. But Faith points out that one of the functions of the VEE—optimizing backlight intensity for the ambient light conditions by manipulating the contrast, rather than simply by cranking up the backlight—could potentially save more energy than the VEE block is consuming.