Practical Chip Design

There have been so many point issues with advanced digital process nodes that the resulting scramble to come up with solutions has been less than obviously organized. Some teams have worked on improving tool speed and capacity, while others have worked on adapting algorithms to multicore processing. Yet other teams have tried to adapt analysis tools to the multi-corner, multi-mode style of analysis necessary in advanced designs, while others still have pursued statistical techniques for timing analysis in the hope of avoiding the proliferation of corners. Another branch of the industry has been working on closer integration of digital and analog flows, in anticipation of the high-performance mixed-signal blocks that will certainly end up in some of the advanced ICs. And yet others have struggled to raise a recalcitrant umbrella of system-level estimation and design tools over the whole jumbled process.

While this fragmented approach to tool development may be necessary in order to get the right set of expertises on the right problems, it is clearly no way to take a new capability to market. And so Cadence today is trying to bring together a whole basket of improvements, adaptations, and new capabilities under a single brand: the Encounter Digital Implementation System. Targeted at 45 nm and smaller geometries, the System tries to anticipate and address the majority of the new problems teams will encounter at these geometries across the entire flow.

Underlying everything is what Cadence claims is the first complete end-to-end support for multicore computing among digital design flows. This means not only that each individual algorithm has been reorganized for distribution across CPU cores in a shared-cache multicore processor chip, but that significant work has gone into reducing the memory footprint of the most memory-retentive applications to make such operation feasible on the kinds of workstations most users actually have in front of them.

Naturally Cadence has included in the flow their latest thinking on analysis tools, statistical timing, low-power design, power and thermal analysis, and the like. It appears that as much as feasible at this stage they are attempting to use common engines for early estimation, analysis, and sign-off, but these questions are tough to answer in a short presentation. And like an earlier announcement by Synopsys, Cadence is working to wire the Digital Encounter and Virtuoso platforms into a single cockpit.

There is also work on early estimation and planning tools, to try to herd the iterations into the front end of the design process. These are to some extent based on Cadence's acquisition of ChipEstimate.com, but appear to include some new things as well, such as early power rail analysis. Of course design-for-manufacturing practices are embedded throughout the flow. And there has apparently been considerable work on the sign-off phase of the flow as well, including such issues as extending the capacity of sign-off analysis tools to handle a whole 32 nm design, and incorporating new capabilities, such as modeling of local thermal variations, into the sign-off process. "Design teams are telling us that they are encountering 20-40 C temperature variations across a die during operation, and even significant temperature differences between metal layers," says Rahul Deokar, product marketing director at Cadence.