Practical Chip Design

The ordinary life cycle for a proprietary I/O scheme begins with its creation to solve a specific design problem. If the product becomes widely used, the interface may get embedded in an application space and become a de-facto standard, remaining until it grows unserviceably obsolete. But if the vendor behind the spec is powerful enough, the bus may survive and evolve, gaining performance and features to support new generations of needs. For examples, consider the evolution of PCI into PCI Express gen-X, or, for our purposes here, the course of RapidIO.

You can trace the inception of RapidIO to the point at which DSP designers realized that they had painted themselves into a bandwidth corner by thinking of DSP cores as chips rather than as IP. But the basic concept of a packet-switched network based on a point-to-point physical link spread throughout the DSP world and its near neighbor, the FPGA world, became intertwined with TI DSP chips, and so has continued to evolve through the transition from parallel to serial, and through several improvements in signaling and speed.

Now, perhaps rather belatedly, the sRIO standard is evolving again, in part due to changing user needs and in part, one suspects, due to crushing competition from PCI Express. The result is—predictably—Serial RapidIO Gen2. The new spec calls for twice the maximum bit rate of sRIO 1.3: 20 Gbits/s per lane based on a signaling speed of 6.25 Gbaud/lane. But the changes go beyond raw speed. Gen 2 defines up to 9 virtual channels and equips them with guaranteed minimum bit rates, creates a special Continuous Transmission Virtual Channel type, and demands much more complex flow control.

The Gen2 effort has been going on for some time. But it made the news this week when IDT announced—with remarkably few details—a program to support the new standard. What does appear certain at this point is that IDT has an IP core design for a Gen2 endpoint, and that TI is in the process of pre-silicon interoperability testing with the IP. From there things get less clear. IDT is apparently working on a Gen2 switch chip family, but there are as yet no announcements or hints at a schedule—just hints. "Our money is in selling switches, not IP," offered senior product manager Devashish Paul.

Clearly, though, the company has put a lot of thought into the hardware requirements of a switch. There is certainly added complexity from the additional handshaking used in the new flow-control protocol. But that doesn't seem to be the entire focus of IDT's effort. "We're looking at supporting the Virtual Channels," elaborated product manager Trevor Hiatt. "There are two separate issues there: guaranteed bandwidth and continuous transmission."

Guaranteeing bandwidth, Hiatt suggested, may require separate buffering and schedulers for each Virtual Channel, which has obvious implications for die size. Yet the more interesting issue may be Continuous Transmission. In this mode, the originating endpoint just keeps pumping out a stream of packets into a Virtual Channel that guarantees to carry them at a specified bandwidth. In ordinary sRIO, all packets are tracked to their destination, and if one doesn't show up the network issues a retry command. But in Continuous mode, there are no retries: it's guaranteed bandwidth, but best-effort delivery. The theory is that for media streams such as HDTV or HD Audio, the latency hit from a series of retries would be more damaging to the data than simply dropping a few packets. "So the switch has to not request retransmission," Hiatt said.

Along with the new functional features come new signal-processing requirements. "The programmable pre-emphasis and equalization are more sophisticated than what we had in 1.3," Paul said. Hiatt added: "The spec requires a decision-feedback equalizer at the 6.25 rate, but we have included continuous-time equalization as well." The additions are probably necessary to achieve Gen2's speed and extended reach of up to 100cm through two connectors. Along with the more complex signaling comes the need for more powerful debug support. The IDT design includes an on-die virtual 'scope, self-test capabilities, and both mandated and proprietary error-management facilities.

Will all this permit sRIO to hold off the charge from Intel-backed PCI Express as it rolls into Gen2 and on to Gen3? It's an open question, of course. But sRIO does have some innate advantages, according to the IDT team. Paul cites power as one such. Power consumption has improved in Gen2 over 1.3, but inherently sRIO has a power advantage just because its headers are simpler. "The headers are more efficient, and this is significant for packets up to 256 Bytes," he said. And there is the matter of latency. The standard claims, by its measurements, the shortest cut-through latency available in any embedded protocol.