Practical Chip Design

The Hot Interconnects session yesterday that explored photonic alternatives to interconnect for many-core processors and SoCs also produced a paper that approached the same problem from an entirely different direction: a blend of conventional routing and fast global electrical lines to create an hybrid NoC (network on chip.)

The paper, a joint product of researchers at Princeton, Oregon State University, and the University of Texas, Austin, began with the argument that there are two fundamentally different classes of problems in establishing a NoC for chips with large numbers of cores. One class of problems involves moving the very large data streams that might traverse such chips—the data plane problem. The other involves the low-latency, short transactions necessary to synchronize and direct these data flows—the control plane problem.

The researchers argued that the kind of dense, point-to-point local interconnect that is used today in multicore IC designs is just fine for the data plane problem. The large number of parallel interconnect segments and very high speed allows this local interconnect to deal with the massive bandwidth requirements, and the fact that the links are point-to-point, traveling locally between memories, processor cores, and routing boxes, allows a great deal of concurrency. But such routing has a timing weakness, the authors observed. Long lines require multiple clock cycles, since RC delays limit propagation to about 300 ps/mm. Simultaneity across a die becomes very difficult.

The researchers proposed an alternative—current-sensing, feed-forward structures, which can achieve 50 ps/mm propagation delay with 3-6 Gbit/s signals at reasonable wire densities—much more dense than conventional on-chip transmission line structures. Such connections, the paper argued, were fast enough to achieve one-cycle communication across most of a die, and could be used to create a novel multiple-access medium for the control plane.

The novelty of this proposal came not so much from the feed-forward interconnect, but from combining this structure with conventional interconnect to create an hybrid circuit-switching virtual network. The concept is to use the conventional local interconnect to create a mesh network of routing boxes with local parallel links between neighbors. Each routing box would perform the standard routing pipeline: decoding the destination, choosing a path to the next box, buffering the data, and sending it along.

The feed-forward control-plane connections are used to set up and take down virtual circuits within this mesh. This process includes establishing the presence of an available buffer downstream and bypassing the decoding and buffering stages on intermediate routing blocks, so the data zips through intermediate blocks, bypassing most of their internal pipelines, and lands in a block that had a buffer available. Because the control-plane connections are effectively single-cycle, it is possible to dynamically control flow of data on the data plane, with data bypassing the buffers in routing blocks until they reach their intended buffer.

The notion of using a synchronous control plane and a circuit-switched data plane appears interesting, as does the use of a novel control-plane interconnect structure that can be denser than transmission lines. But the underlying notion, that interconnect on multicore chips will more and more resemble large-scale communications networks and less and less resemble microprocessor busses, may be the more enduring idea here.