Practical Chip Design

System-in-Package design has been growing up in a no-mans land. SiPs require circuit design, simulation, routing, extraction, and closure, just like ICs or PCBs. But neither the tools from the chip design world nor the traditional PCB tools are really appropriate to the problems of SiP designers. On the principle that every missing link is a business opportunity, Cadence announced today that it is providing significant support for SiP design, along with significant strengthening of its support for high-density, high-speed PCBs, in its Allegro 16.2 release.

There are new features, based on Cadence's assessment of the problems of the SiP designer. Paramount among the challenges, obviously, is that the spacing used in SiPs—both internally and at the interface to the board—are well into the land of high-density interconnect: defined by cadence as anything less than 0.8 mm pitch. So the 16.2 release supports HDI. But high-density array packages are forcing board designers into this world as well, even if the rest of their designs aren't particularly space-constrained. So 16.2 will offer HDI not just for SiPs, but for boards.

Another point Cadence determined is that SiP design is, like board design, becoming too complex to do in a cut-and-try fashion. It's not feasible any longer for a designer to give a set of requirements his best initial shot, extract models from the result, simulate, and then iterate the whole process. The flow needs to be constraint-driven from the beginning, so that the tools, not just the experience of the designers, are responsible for creating structures that comply with the design requirements. Hence 16.2 offers a constraint-driven flow. For example, the tool set provides guidelines during layout to assist designers in meeting impedance and ripple specifications on power grids, using tools imported from the PCB analysis world. Designers can also write hard constraints for power or signal traces in terms of width and spacing as well as in terms of electrical parameters.

For RF designers, a bi-directional interface to the Agilent ADS tool set allows RF designers to create layout changes, and see the results, directly in the PCB or SiP design environment. This avoids hugely expensive iterations between two engineering teams who tend to have minimal understanding of each other's worlds.

Also with growing complexity, SiP, and board, design teams are getting larger and more dispersed. So the new release offers design partitioning either by layer or by slice, allowing team members in different locations to work in parallel on different portions of the design while maintaining coherency.

There are also specific technical challenges that the new release addresses. One of these is the diversity of input and output models that a design team may have to deal with in a stack of dice from different vendors. By providing an algorithmic modeling interface, proposed as IBIS 5.0, the release allows incorporation of executable models beyond simple IBIS structures. This is particularly vital, according to group director of product marketing Keith Felton, when the design team is using the highly-programmable high-speed serial I/Os now in fashion. The drivers in these sets may offer programmable edge rates, drive strengths, and pre-emphasis, while the receivers may support programmable gain, thresholds, and equalization. A parameterized, algorithmic model may be the only way to predict the behavior of these structures, either within the SiP—where they may be tuned down to save power and avoid what Felton referred to as "horrendous termination networks."

The same problem can occur on the board, where the transceivers may be cranked up, but may turn out to be incompatible with the transceivers on other devices. "The ability to run fast algorithmic models allows you to do enough cycles to get accurate bit error rate estimates," observed PCB director of product marketing Hemant Shah. "That may be the only way you find out about a transceiver incompatibility before you build a prototype."

Another key issue within the SiP, at least with the technology most designs use today, is coping with wirebond impedances. The length and shape of wirebond loops of course varies hugely with the location of the pads, the commands given to the bonding machine, its state of adjustment, and the quality control of the operation. So assuming any simple model for wirebond impedance is, at high frequencies and densities, futile.

Accordingly, Cadence has worked with equipment maker Kulicke & Soffa to provide a library of appropriate models. "We got the definitions of the profiles from K&S, did 3D extractions, and built up S-parameter and RLC libraries," explained Felton. In addition the new release helps select appropriate profiles based on the signal requirements and pad locations in the die stack, and identifies potential wirebond conflicts using a 3D analysis, another instance of constraint-driven flow. Cadence is now talking with other makers of wirebond equipment about similar relationships.

Providing the ability to design to constraints has meant linking what was once an isolated PCB package to analysis tools that were not always associated with the PCB designer's job. In a way, PCB and SiP design environments are becoming cockpits from which an engineer can access a wide range of models, analytical tools and design-creation tools. This reflects the changing nature of SiP designers, and to a great extent PCB designers, according to Felton. "We aren't seeing this work done by PCB specialists who are just polygon-pushers. These days PCB design, and certainly SiP design, are the province of young engineers capable of doing the whole job, including layout, geometric and electrical checks, and manufacturability analysis. The days of just making a piece of art and sending it back to the electronic design team for analysis are over."

And equally nearing the end, apparently, are the distinctions between board and package design. With a release targeting both worlds, Cadence is underlining the observation that no longer can we regard PCB design as somehow a simple process, and package design as a mechanical problem. With passive components migrating off of silicon dice and into packages or boards, with high-density three-dimensional structures that are electrically part of the circuit design, and with even higher speeds and densities on the horizon, this is a new world. The next big question is how the tools will track the migration from today's stack-die, wire-bonded SiPs to the true 3D IC concepts now working in labs around the world. Stay tuned.