Practical Chip Design

The event of interest in Silicon Valley this morning was the annual Research@Intel Day, in which the various research teams at Intel's ten R/D centers around the world get to do Show and Tell for the press. There's much to ponder about the event, but first I should focus on an invited guest who is not, strictly speaking, part of the Intel Corporate Technology Group. Mike Mayberry, vice president of the Technology and Manufacturing Group, describes the distinction between his organization and what's now called Intel Labs as follows: "Technology and Manufacturing does the process R/D and runs all the Intel manufacturing facilities. Intel Labs' job is to figure out what we should build, and how users would live with it if we did."

Despite the organizational difference, Mayberry was at the event this morning hosting a round-table discussion on manufacturing research. While he only had a few minutes to speak before Q/A, Mayberry presented a pretty effective view, through a series of vignettes, of Intel's process roadmap through the next few years.

To begin with the near-term, the VP said that Intel will begin production on their 32 nm process this year. That process will use immersion lithography, and apparently a version of the company's existing high-k/metal-gate gate stack. Intel appears to have anticipated leakage problems with transistors below 40 nm some time ago, and decided to make the move to high-k/metal-gate earlier than necessary. As a consequence, they now have production experience with a gate architecture that still appears to be giving other companies fits—TSMC, for instance. And so the strategy of making change early, but not often, seems to be playing out well.

But at this point, 32 nm is no longer a research issue. "Our internal research focuses on things that will hit production in three to seven years," Mayberry explained. "For things longer-term than that, we mainly rely on outside research partnerships, with universities, or with the IMEC or Sematech consortia." So Mayberry's process development people are putting the finishing touches on 32 nm, while his research teams are working on nodes further out.

The big question for those nodes further out is lithography. Intel has by now made a huge investment in EUV, but Mayberry was distinctly circumspect about when—if ever—EUV would be a production technology for the company. The good news, he said, is that Intel is now printing 24 nm features with their internally-done masks and the ASML EUV Alpha-steppers. But there are still many problems to be resolved to push that limit out beyond the range accessible to optical lithography.

One issue is resolution. The big machines still aren't producing patterns that can't be done in the lab with 193 nm equipment. But a potentially more serious problem—still—is illumination. Existing EUV sources have been so dim that exposing one production wafer takes a significant fraction of an hour. Mayberry said that the Cymer source is now bright enough to potentially reach 10 wafer/hour throughput, but this is still far below break-even for a production printer. "That's phase 2," Mayberry said. "We need to get to phase 3, where we have enough intensity for production throughput."

In fact, he added, the Cymer source has demonstrated enough beam energy to achieve production throughput—but only in short pulses. It cannot operate continuously at the required illumination levels, as would be required of a production source. And no one is willing to say unequivocally that either of the existing sources can scale to continuous use.

Making the issue more critical is the enormous progress in extending 193 nm lithography. Mayberry showed a foil illustrating both interleaved-pattern double-patterning and computational lithography. In the latter case, Intel is working with pixilated masks. There are serious issues with both of these technologies, not least of which is cost. Obviously double-patterning means two passes through the lithography equipment. And computational lithography means a lot of computation—Mayberry said that Intel's initial efforts required a million CPU hours to compute a mask. "But we've improved quite a bit since then," he added.

The capabilities of such technologies are potentially excellent. "In the lab, we have been able to create simple patterns—lines and spaces—in the range of 15 nm with these techniques and 193 nm equipment," Mayberry said. It may very well be that by the time EUV is ready for production, 193 nm will already have passed it by.

Mayberry also discussed Intel work in new materials. The company is exploring III-V compounds—specifically, InGaAs and InSb, to achieve higher carrier mobility at fine geometries. "These are materials that may go into production in the middle of the next decade," Mayberry said. "Right now, we are building a list of grand challenges in using them."

There is also work on the interconnect stack. "We are very happy with copper," Mayberry emphasized. "But by the time you have a line 10 nm wide, the dominant effect isn't conduction, its edge scattering. We will need both new dielectrics and new metal systems as we go along."

And of course there is memory. Mayberry said that Intel is working on three novel memory technologies in parallel: floating-body memory, phase-change memory, and seek-and scan probe memory. These are listed in approximate order of difficulty and density—with floating-body being fairly near-term and seek-and-scan pretty researchy. Asked about density, Mayberry estimated that a floating-body cell would be about 0.01 µm², while a phase-change memory cell could in principle be even smaller: about 4 minimum feature lengths on a side. Intel has created seek-and-scan memory arrays in which the individual bit cells are about 9 nm on a side, he said. As of today, Intel has delivered some engineering devices of the phase-change memory to prospective customers, purely to get their feedback on what characteristics they would like to see in such a device. There appears to be no productization plan for any of the three any time soon.

One final intriguing note, mentioned by CTO Justin Rattner at the beginning of the event and explained in more detail by Mayberry, concerns Intel's interest in the intersection of biology and nanoelectronics. This, by the way, is an interest strongly shared with the IMEC consortium. Rattner alluded to a "transistor-like device" that could traverse a strand of DNA, reading off the sequence of the amino acids as it went.

Mayberry described a similar concept: a device with a molecular template engraved in its surface, and underlying circuitry that cause a change in electrical characteristics when an organic molecule fits into the template. "There are really two parts to this problem," Mayberry explained. "You have to prepare a template and layer it over the electronics. Then when you get a signal indicating that a molecule has fitted into the template, it's a very low-level signal embedded in a great deal of noise. You have to have a lot of signal-processing power to extract it."

So device and process development is moving along on many fronts: lithography, materials, and devices. Notable by its absence was any mention of finFET devices—whether because of time constraints or because Intel is no longer pursuing them I couldn't say.