Practical Chip Design

TSMC today announced their Reference Flow 9.0, targeted at customers developing chips for the 45 and 40 nm processes. In many ways, 9.0 is a statement on how well the previous reference flow, for 65 nm, anticipated the problems of very deep sub-micron design. But there are a few major departures from the previous flow, and each of them has something to day about the realities of working at 40 nm.

The first thing to notice is that statistical analysis tools have entered the flow in a big way. TSMC is now supporting the Apache Design statistical thermal analysis package, and both the CLK Design Automation and the Extreme DA statistical timing tools.

As discussed elsewhere, these two products differ in their approach to the problem. The CLK Amber FX is unique in that it works at the transistor level, first building up statistics on the cells in the user's library from the transistor-level cell descriptions and the foundry's transistor models, then searching out and performing statistical analyses on the design's critical paths. Extreme DA's GoldTime works at the cell level, doing statistical characterization of the cells and of the extracted interconnect parameters.

TSMC deputy director of design services marketing Tom Quan explained that the company chose to include both tools in the flow. "Cell-based statistical tools require pre-characterization of the libraries, which can be a bottleneck early in the life of a process node," he said. "The CLK tool does not require this. But we simply don't have enough experience with these new tools to recommend one over the other at this point. We think people should look at the size of their design, at the speed of the tools, and at their accuracy, and come to their own decision about which statistical approach to use."

But Quan leaves no doubt that statistical analysis is coming. "We are still doing timing sign-off using multi-mode, multi-corner static analysis," he admits. "But I think you will see us moving to a combination of corner-based analysis and statistical analysis even for sign-off."

Underlying the shift to statistical tools is an enormous amount of data mining and characterization work on the new process—probably more than has been done on a production process before. The company has had to provide statistics files for its already-detailed transistor and interconnect models, and include data on multi-layer variation effects, and on the relationship between shape and thickness variations—the things fab teams always worry about—and electrical variations, which fabs in the past have left up to chip designers.

Other significant changes relate to the increased concern for power management. TSMC has added tools to its power management flow, including power-driven advanced clock gating and power-aware clock tree synthesis, and they will continue to offer the PowerTrim service based on BlazeDFM.

And of course there are changes that may reflect politics as much as technology. One such is that TSMC will now support the Unified Power Format as well as the Common Power Format, coming down squarely in the middle of one of those industry format debates. Another is that the 9.0 flow is transparent to the difference between TSMC's originally-announced 45 nm geometry and it's now-claimed 40 nm geometry. While industry opinion differs as to whether there are real physical differences on the die or in the process between the two nodes, TSMC intends to make the question moot. Designers can design for 45 nm if they wish, and then decide to implement in the 40 nm rules at the end of the flow.  This is possible basically by providing tech files in the PDK that are scaled to support either geometry.