Practical Chip Design

Solido Design has, as previously projected, added another tool to their Variation Designer platform. Well-Proximity is the first tool in a second package that runs on the Variation Designer Platform, complementing the Statistics package.

The well-proximity issue, according to Solido corporate applications engineering manager Kristopher Breen, becomes an important source of process variations at 90 nm. But to date, most design teams have either been ignoring the effect—risking significant yield loss or outright design failures in their analog and custom circuits—or they have been inserting guard-band spacing around the edges of well implants, trading die area for safety.

The mechanism that produces these variations is fairly interesting. Today's processes form wells of doped silicon in which the transistors will sit. The wells are formed by doing an implant of energetic ions through the openings in a photomask. Ideally, ions would pass through the openings in the mask, lodge in the wafer and form the doped silicon that defines the wells. The ions that strike the photoresist mask material should get reflected or absorbed. But because this is a relatively high-energy implant—in order to quickly get the wells deep enough—some of the ions that strike the edges of the resist around the openings scatter within the resist material and end up bouncing into the well area. This mechanism leaves a halo of slightly higher-doped silicon around the edges of the well. If you locate a transistor in this halo region, it will have a more highly-doped channel that the transistors further from the edge of the well. Hence, it will show variations in performance.

The obvious solution, to paraphrase an old Groucho Marx line, is simply don't put transistors there. That is basically what the foundry recommended design rules say, often specifying a 3 µ guard band around the perimeter of every well. But all that area adds up over the course of a design. So some analog design teams take a more measured approach. They ignore the well-proximity spacing rule and lay out their transistors as if the effect didn't exist. Then during the post-layout extraction they plug in the values for well-proximity thoughtfully provided in the foundry models, simulate, and see if the circuit still works. If it doesn't, they go back and adjust the devices near the edges of the wells.

This makes a lot of sense area-wise, since the majority of transistors will not need to be adjusted, according to Breen. But it means an extra design task after extraction—worse, a task that can require adjusting the layout or resizing transistors. Given all the other things that can be going on during this cycle, another task is not welcome news.

Solido's Well-Proximity plug-in offers—you've already guessed, haven't you?—an alternative. Working next to the variation-predicting tools in Solido's Statistics package, Well Proximity uses the proximity-effect parameters in the foundry transistor models to, in effect, do a sensitivity analysis on each transistor in your design. As described in outline by Breen, the tool adjusts the well-proximity model parameters on a transistor to correspond to moving the transistor closer to the well edge. It then runs a circuit simulation to see if this has made a significant difference in the circuit performance. If the circuit is OK, the tool moves the transistor closer, and so on, until it reaches minimum spacing. If moving the transistor close to the well edge causes a circuit change, the tool marks the transistor as critical, passing this information to the layout designers.

The result, according to Breen, is that most of the analog transistors in your design end up not marked as critical. So the layout engineer has a lot of freedom to place transistors with minimum spacing, only using guard-band spacing when it makes a difference to the circuit performance. The bottom line, of course, is a smaller die, without the risk of yield loss from well-proximity effects.